[PATCH] Recognize RISC-V compilation targets.

[PATCH] Recognize RISC-V compilation targets.

[Shea Levy]

* module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants.

Signed-off-by: Shea Levy <shea@shealevy.com>
---
 module/system/base/target.scm | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/module/system/base/target.scm b/module/system/base/target.scm
index 95ab8d8c9..93616f4a3 100644
--- a/module/system/base/target.scm
+++ b/module/system/base/target.scm
@@ -86,6 +86,8 @@
              (endianness big))
             ((string=? "aarch64" cpu)
              (endianness little))
+            ((string-match "riscv[1-9][0-9]*" cpu)
+             (endianness little))
             (else
              (error "unknown CPU endianness" cpu)))))
 
-- 
2.16.1

Re: [PATCH] Recognize RISC-V compilation targets.

[Shea Levy]

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Hi all,

Any thoughts on this?

Thanks,
Shea

Shea Levy <shea@shealevy.com> writes:

> * module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants.
>
> Signed-off-by: Shea Levy <shea@shealevy.com>
> ---
>  module/system/base/target.scm | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/module/system/base/target.scm b/module/system/base/target.scm
> index 95ab8d8c9..93616f4a3 100644
> --- a/module/system/base/target.scm
> +++ b/module/system/base/target.scm
> @@ -86,6 +86,8 @@
>               (endianness big))
>              ((string=? "aarch64" cpu)
>               (endianness little))
> +            ((string-match "riscv[1-9][0-9]*" cpu)
> +             (endianness little))
>              (else
>               (error "unknown CPU endianness" cpu)))))
>  
> -- 
> 2.16.1

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Re: [PATCH] Recognize RISC-V compilation targets.

[Mark H Weaver]

Hi Shea, sorry for the delay.

Shea Levy <shea@shealevy.com> writes:
> * module/system/base/target.scm (cpu-endianness): Add case for "riscv"
> variants.

Applied in commit 08bb4628369cf3efe7c96a32919705c41a9ed9e9 of the
stable-2.2 branch, so it will be included in Guile-2.2.4.

Thank you for working on RISC-V.  That project gives me hope :)

     Mark

Re: [PATCH] Recognize RISC-V compilation targets.

[Shea Levy]

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Great, thanks! I'm fairly new to the project myself, and seeing how well
things are progressing and the quality of the team has inspired me as
well :)

~Shea

Mark H Weaver <mhw@netris.org> writes:

> Hi Shea, sorry for the delay.
>
> Shea Levy <shea@shealevy.com> writes:
>> * module/system/base/target.scm (cpu-endianness): Add case for "riscv"
>> variants.
>
> Applied in commit 08bb4628369cf3efe7c96a32919705c41a9ed9e9 of the
> stable-2.2 branch, so it will be included in Guile-2.2.4.
>
> Thank you for working on RISC-V.  That project gives me hope :)
>
>      Mark

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