From: Shea Levy <shea@shealevy.com>
To: Mark H Weaver <mhw@netris.org>
Cc: guile-devel@gnu.org
Subject: Re: [PATCH] Recognize RISC-V compilation targets.
Date: Fri, 16 Mar 2018 09:07:57 -0400 [thread overview]
Message-ID: <871sgkyxqq.fsf@xps13.shealevy.com> (raw)
In-Reply-To: <87605w671b.fsf@netris.org>
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Great, thanks! I'm fairly new to the project myself, and seeing how well
things are progressing and the quality of the team has inspired me as
well :)
~Shea
Mark H Weaver <mhw@netris.org> writes:
> Hi Shea, sorry for the delay.
>
> Shea Levy <shea@shealevy.com> writes:
>> * module/system/base/target.scm (cpu-endianness): Add case for "riscv"
>> variants.
>
> Applied in commit 08bb4628369cf3efe7c96a32919705c41a9ed9e9 of the
> stable-2.2 branch, so it will be included in Guile-2.2.4.
>
> Thank you for working on RISC-V. That project gives me hope :)
>
> Mark
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prev parent reply other threads:[~2018-03-16 13:07 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-26 1:34 [PATCH] Recognize RISC-V compilation targets Shea Levy
2018-03-15 13:23 ` Shea Levy
2018-03-16 3:20 ` Mark H Weaver
2018-03-16 13:07 ` Shea Levy [this message]
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