From: Shea Levy <shea@shealevy.com>
To: guile-devel@gnu.org
Subject: Re: [PATCH] Recognize RISC-V compilation targets.
Date: Thu, 15 Mar 2018 09:23:40 -0400 [thread overview]
Message-ID: <87a7v9zd43.fsf@xps13.shealevy.com> (raw)
In-Reply-To: <20180226013439.9461-1-shea@shealevy.com>
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Hi all,
Any thoughts on this?
Thanks,
Shea
Shea Levy <shea@shealevy.com> writes:
> * module/system/base/target.scm (cpu-endianness): Add case for "riscv" variants.
>
> Signed-off-by: Shea Levy <shea@shealevy.com>
> ---
> module/system/base/target.scm | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/module/system/base/target.scm b/module/system/base/target.scm
> index 95ab8d8c9..93616f4a3 100644
> --- a/module/system/base/target.scm
> +++ b/module/system/base/target.scm
> @@ -86,6 +86,8 @@
> (endianness big))
> ((string=? "aarch64" cpu)
> (endianness little))
> + ((string-match "riscv[1-9][0-9]*" cpu)
> + (endianness little))
> (else
> (error "unknown CPU endianness" cpu)))))
>
> --
> 2.16.1
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next prev parent reply other threads:[~2018-03-15 13:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-26 1:34 [PATCH] Recognize RISC-V compilation targets Shea Levy
2018-03-15 13:23 ` Shea Levy [this message]
2018-03-16 3:20 ` Mark H Weaver
2018-03-16 13:07 ` Shea Levy
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