From: Mark H Weaver <mhw@netris.org>
To: Shea Levy <shea@shealevy.com>
Cc: guile-devel@gnu.org
Subject: Re: [PATCH] Recognize RISC-V compilation targets.
Date: Thu, 15 Mar 2018 23:20:00 -0400 [thread overview]
Message-ID: <87605w671b.fsf@netris.org> (raw)
In-Reply-To: <20180226013439.9461-1-shea@shealevy.com> (Shea Levy's message of "Sun, 25 Feb 2018 20:34:39 -0500")
Hi Shea, sorry for the delay.
Shea Levy <shea@shealevy.com> writes:
> * module/system/base/target.scm (cpu-endianness): Add case for "riscv"
> variants.
Applied in commit 08bb4628369cf3efe7c96a32919705c41a9ed9e9 of the
stable-2.2 branch, so it will be included in Guile-2.2.4.
Thank you for working on RISC-V. That project gives me hope :)
Mark
next prev parent reply other threads:[~2018-03-16 3:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-26 1:34 [PATCH] Recognize RISC-V compilation targets Shea Levy
2018-03-15 13:23 ` Shea Levy
2018-03-16 3:20 ` Mark H Weaver [this message]
2018-03-16 13:07 ` Shea Levy
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