From: Ekaitz Zarraga <ekaitz@elenq.tech>
To: 68222@debbugs.gnu.org
Cc: Ekaitz Zarraga <ekaitz@elenq.tech>, janneke@gnu.org
Subject: [bug#68222] [PATCH 0/3] RISC-V support to commencement until tcc-boot0
Date: Tue, 2 Jan 2024 21:02:31 +0100 [thread overview]
Message-ID: <cover.1704225349.git.ekaitz@elenq.tech> (raw)
This patch set adds RISC-V support to the commencement (aka bootstrap) process
from the begining to tcc-boot0 (included).
Ekaitz Zarraga (3):
gnu: stage0-posix: Update to 1.6.0
gnu: mes-boot: Update to 0.25.1.
gnu: tcc-boot0: Update to 0.9.26-1151-g9b4a5d90.
gnu/packages/commencement.scm | 137 +++++++---------------------------
1 file changed, 26 insertions(+), 111 deletions(-)
base-commit: e8814809c2de6fe2f23169775207b3d2e537724f
--
2.41.0
next reply other threads:[~2024-01-02 20:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-02 20:02 Ekaitz Zarraga [this message]
2024-01-02 20:04 ` [bug#68222] [PATCH 1/3] gnu: stage0-posix: Update to 1.6.0 Ekaitz Zarraga
2024-01-02 20:04 ` [bug#68222] [PATCH 2/3] gnu: mes-boot: Update to 0.25.1 Ekaitz Zarraga
2024-01-02 20:04 ` [bug#68222] [PATCH 3/3] gnu: tcc-boot0: Update to 0.9.26-1151-g9b4a5d90 Ekaitz Zarraga
2024-01-11 16:36 ` [bug#68222] [PATCH 0/3] RISC-V support to commencement until tcc-boot0 Ekaitz Zarraga
2024-01-11 16:37 ` Ekaitz Zarraga
2024-01-12 10:44 ` bug#68222: " Efraim Flashner
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