;;; GNU Guix --- Functional package management for GNU
;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org>
;;;
;;; This file is part of GNU Guix.
;;;
;;; GNU Guix is free software; you can redistribute it and/or modify it
;;; under the terms of the GNU General Public License as published by
;;; the Free Software Foundation; either version 3 of the License, or (at
;;; your option) any later version.
;;;
;;; GNU Guix is distributed in the hope that it will be useful, but
;;; WITHOUT ANY WARRANTY; without even the implied warranty of
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;;; GNU General Public License for more details.
;;;
;;; You should have received a copy of the GNU General Public License
;;; along with GNU Guix.  If not, see <http://www.gnu.org/licenses/>.

(define-module (gnu packages fpga)
  #:use-module ((guix licenses) #:prefix license:)
  #:use-module (guix packages)
  #:use-module (guix download)
  #:use-module (guix git-download)
  #:use-module (guix build-system gnu)
  #:use-module (guix build-system cmake)
  #:use-module (gnu packages)
  #:use-module (gnu packages pkg-config)
  #:use-module (gnu packages tcl)
  #:use-module (gnu packages readline)
  #:use-module (gnu packages python)
  #:use-module (gnu packages bison)
  #:use-module (gnu packages flex)
  #:use-module (gnu packages libffi)
  #:use-module (gnu packages zip)
  #:use-module (gnu packages perl)
  #:use-module (gnu packages ghostscript)
  #:use-module (gnu packages gawk)
  #:use-module (gnu packages version-control)
  #:use-module (gnu packages libftdi))

;; To compile as C code (default):
;;   make sure that CC=gcc and ABC_NAMESPACE is not defined.
;; To compile as C++ code with namespaces:
;;   make sure that CC=g++ and ABC_NAMESPACE is set to the namespace.
;;   For example, add -DABC_NAMESPACE=xxx to OPTFLAGS.
(define-public abc
 (let ((commit "5ae4b975c49c"))
  (package
    (name "abc")
    (version (string-append "0.0-" (string-take commit 7)))
    (source (origin
              (method url-fetch)
              (uri
               (string-append "https://bitbucket.org/alanmi/abc/get/"
                              commit ".zip"))
              (file-name (string-append name "-" version "-checkout.zip"))
              (sha256
                (base32
                   "1syygi1x40rdryih3galr4q8yg1w5bvdzl75hd27v1xq0l5bz3d0"))))
    (build-system gnu-build-system)
    (native-inputs
     `(("unzip" ,unzip)))
    (inputs
     `(("readline" ,readline)))
    (arguments
     `(#:tests? #f ; 'check target does not exist.
       #:phases
        (modify-phases %standard-phases
          (delete 'configure)
          (replace 'install
            (lambda* (#:key outputs #:allow-other-keys)
              (let* ((out (assoc-ref outputs "out"))
                     (outbin (string-append out "/bin"))
                     (target (string-append outbin "/abc")))
                    (mkdir-p outbin)
                    (copy-file "abc" target)))))))
    (home-page "http://people.eecs.berkeley.edu/~alanmi/abc/")
    (synopsis "Sequential Logic Synthesis and Formal Verification")
    (description "ABC is a program for sequential logic synthesis
and formal verification.")
    ;; FIXME use license: MIT Modern variant as described in:
    ;;   <https://fedoraproject.org/wiki/Licensing:MIT>
    (license license:expat))))

(define-public iverilog
  (package
    (name "iverilog")
    (version "10.1.1")
    (source (origin
              (method url-fetch)
              (uri
               (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/verilog-" version ".tar.gz"))
              (sha256
                (base32
                   "1nnassxvq30rnn0r2p85rkb2zwxk97p109y13x3vr365wzgpbapx"))))
    (build-system gnu-build-system)
    (native-inputs
     `(("flex" ,flex)
       ("bison" ,bison)
       ("ghostscript" ,ghostscript) #| ps2pdf |#))
    (home-page "http://iverilog.icarus.com/")
    (synopsis "FPGA Verilog Simulation and Synthesis Tool")
    (description "Icarus Verilog is a Verilog simulation and synthesis tool.
It operates as a compiler, compiling source code written in Verilog
(IEEE-1364) into some target format.
For batch simulation, the compiler can generate an intermediate form called
vvp assembly.
This intermediate form is executed by the ``vvp'' command.
For synthesis, the compiler generates netlists in the desired format.")
    (license license:gpl2)))