* [bug#57291] New package: fftgen
@ 2022-08-18 23:18 Gabriel Wicki
2022-09-02 15:29 ` bug#57291: " Ludovic Courtès
2022-09-02 18:57 ` Maxime Devos
0 siblings, 2 replies; 4+ messages in thread
From: Gabriel Wicki @ 2022-08-18 23:18 UTC (permalink / raw)
To: 57291
Hi!
I've stumbled upon this beautiful little piece of software that let's
you generate FFT designs in Verilog. Since it's free software I thought
I'd ready it up for my favorite distribution!
Thanks for merging!
gabriel
From 189ae40cb6104ac703f0171e32fe88208f9fcc25 Mon Sep 17 00:00:00 2001
From: Gabriel Wicki <gabriel@erlikon.ch>
Date: Fri, 19 Aug 2022 01:14:06 +0200
Subject: [PATCH] gnu: Add fftgen.
* gnu/packages/fpga.scm (fftgen): New variable.
---
gnu/packages/fpga.scm | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 06d4a10e7e..e1ae577c65 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -552,3 +552,34 @@ (define-public verilator
performs the design simulation. Verilator also supports linking its generated
libraries, optionally encrypted, into other simulators.")
(license license:lgpl3)))
+
+(define-public fftgen
+ (let ((commit "1d75a992efd0528edea128a903aafdabe133cb08")
+ (revision "0"))
+ (package
+ (name "fftgen")
+ (version (git-version "0" revision commit))
+ (source (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://github.com/ZipCPU/dblclockfft")
+ (commit commit)))
+ (file-name (git-file-name name
+ (string-take commit 8)))
+ (sha256
+ (base32
+ "0qq874yalzpjdwnxhc5df8a0ifywv29wcncb09945x56xplvkcmd"))))
+ (build-system gnu-build-system)
+ (arguments
+ `(#:tests? #f
+ #:phases (modify-phases %standard-phases
+ (delete 'configure)
+ (replace 'install
+ (lambda* (#:key outputs #:allow-other-keys)
+ (let ((bin (string-append (assoc-ref outputs "out")
+ "/bin")))
+ (install-file "sw/fftgen" bin) #t))))))
+ (synopsis "Generic Pipelined FFT Core Generator")
+ (description "fftgen produces FFT hardware designs in Verilog.")
+ (home-page "https://zipcpu.com/")
+ (license license:lgpl3))))
--
2.36.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* bug#57291: New package: fftgen
2022-08-18 23:18 [bug#57291] New package: fftgen Gabriel Wicki
@ 2022-09-02 15:29 ` Ludovic Courtès
2022-09-02 19:00 ` [bug#57291] " Maxime Devos
2022-09-02 18:57 ` Maxime Devos
1 sibling, 1 reply; 4+ messages in thread
From: Ludovic Courtès @ 2022-09-02 15:29 UTC (permalink / raw)
To: Gabriel Wicki; +Cc: 57291-done
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Hi,
Gabriel Wicki <gabriel@erlikon.ch> skribis:
>>From 189ae40cb6104ac703f0171e32fe88208f9fcc25 Mon Sep 17 00:00:00 2001
> From: Gabriel Wicki <gabriel@erlikon.ch>
> Date: Fri, 19 Aug 2022 01:14:06 +0200
> Subject: [PATCH] gnu: Add fftgen.
>
> * gnu/packages/fpga.scm (fftgen): New variable.
Applied with the minor changes below, thanks!
Ludo’.
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diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index e1ae577c65..58b81bf83a 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -554,7 +554,7 @@ (define-public verilator
(license license:lgpl3)))
(define-public fftgen
- (let ((commit "1d75a992efd0528edea128a903aafdabe133cb08")
+ (let ((commit "1d75a992efd0528edea128a903aafdabe133cb08") ;no releases
(revision "0"))
(package
(name "fftgen")
@@ -564,22 +564,23 @@ (define-public fftgen
(uri (git-reference
(url "https://github.com/ZipCPU/dblclockfft")
(commit commit)))
- (file-name (git-file-name name
- (string-take commit 8)))
+ (file-name (git-file-name name version))
(sha256
(base32
"0qq874yalzpjdwnxhc5df8a0ifywv29wcncb09945x56xplvkcmd"))))
(build-system gnu-build-system)
(arguments
- `(#:tests? #f
+ `(#:tests? #f ;no tests
+ #:make-flags '("CFLAGS=-g -O2") ;default flags lack -O2
#:phases (modify-phases %standard-phases
(delete 'configure)
(replace 'install
(lambda* (#:key outputs #:allow-other-keys)
(let ((bin (string-append (assoc-ref outputs "out")
"/bin")))
- (install-file "sw/fftgen" bin) #t))))))
- (synopsis "Generic Pipelined FFT Core Generator")
- (description "fftgen produces FFT hardware designs in Verilog.")
+ (install-file "sw/fftgen" bin)))))))
+ (synopsis "Generic pipelined FFT core generator")
+ (description "fftgen produces @acronym{FFT, fast-Fourier transforms}
+hardware designs in Verilog.")
(home-page "https://zipcpu.com/")
- (license license:lgpl3))))
+ (license license:lgpl3+))))
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [bug#57291] New package: fftgen
2022-08-18 23:18 [bug#57291] New package: fftgen Gabriel Wicki
2022-09-02 15:29 ` bug#57291: " Ludovic Courtès
@ 2022-09-02 18:57 ` Maxime Devos
1 sibling, 0 replies; 4+ messages in thread
From: Maxime Devos @ 2022-09-02 18:57 UTC (permalink / raw)
To: Gabriel Wicki, 57291
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On 19-08-2022 01:18, Gabriel Wicki wrote:
> + (file-name (git-file-name name
> + (string-take commit 8)))
You don't have to string-take, the standard pattern is (git-file-name
name version), as in (guix)Version Numbers.
> + `(#:tests? #f
Why are tests disabled? There is a bench-test target, maybe you need
#:test-target "bench-test"? I hope that means "test bench" and not
"benchmark" though.
On the license: some parts are GPL3+ (see:
https://github.com/ZipCPU/dblclockfft/blob/master/sw/legal.h), that
sounds important to add to the license field to me (license
(license:lgpl3+ license:gpl3+)).
Greetings,
Maxime.
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [bug#57291] New package: fftgen
2022-09-02 15:29 ` bug#57291: " Ludovic Courtès
@ 2022-09-02 19:00 ` Maxime Devos
0 siblings, 0 replies; 4+ messages in thread
From: Maxime Devos @ 2022-09-02 19:00 UTC (permalink / raw)
To: 57291, ludo, gabriel
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On 02-09-2022 17:29, Ludovic Courtès wrote:
> + #:make-flags '("CFLAGS=-g -O2") ;default flags lack -O2
I think (string-append "CXX=" #$(cxx-for-target)) is needed to, for
cross-compilation.
Greetings,
Maxime.
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-09-02 19:01 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2022-08-18 23:18 [bug#57291] New package: fftgen Gabriel Wicki
2022-09-02 15:29 ` bug#57291: " Ludovic Courtès
2022-09-02 19:00 ` [bug#57291] " Maxime Devos
2022-09-02 18:57 ` Maxime Devos
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