[PATCH v2 0/5] Add FPGA Tools

[PATCH v2 0/5] Add FPGA Tools

[Danny Milosavljevic]

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This patch adds FPGA tools.

Danny Milosavljevic (5):
  gnu: Add abc.
  gnu: Add iverilog.
  gnu: Add yosys.
  gnu: Add icestorm.
  gnu: Add arachne-pnr.

 gnu/local.mk          |   1 +
 gnu/packages/fpga.scm | 273 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 274 insertions(+)
 create mode 100644 gnu/packages/fpga.scm

[PATCH v2 1/5] gnu: Add abc.

[Danny Milosavljevic]

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gnu: Add abc.
* gnu/packages/fpga.scm: New file.
* gnu/packages/fpga.scm (abc): New variable.
---
 gnu/local.mk          |  1 +
 gnu/packages/fpga.scm | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 76 insertions(+)
 create mode 100644 gnu/packages/fpga.scm


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diff --git a/gnu/local.mk b/gnu/local.mk
index 53621d8..84aca08 100644
--- a/gnu/local.mk
+++ b/gnu/local.mk
@@ -124,6 +124,7 @@ GNU_SYSTEM_MODULES =				\
   %D%/packages/fltk.scm				\
   %D%/packages/fonts.scm			\
   %D%/packages/fontutils.scm			\
+  %D%/packages/fpga.scm				\
   %D%/packages/freedesktop.scm			\
   %D%/packages/freeipmi.scm			\
   %D%/packages/ftp.scm				\
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
new file mode 100644
index 0000000..f757a28
--- /dev/null
+++ b/gnu/packages/fpga.scm
@@ -0,0 +1,75 @@
+;;; GNU Guix --- Functional package management for GNU
+;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org>
+;;;
+;;; This file is part of GNU Guix.
+;;;
+;;; GNU Guix is free software; you can redistribute it and/or modify it
+;;; under the terms of the GNU General Public License as published by
+;;; the Free Software Foundation; either version 3 of the License, or (at
+;;; your option) any later version.
+;;;
+;;; GNU Guix is distributed in the hope that it will be useful, but
+;;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;;; GNU General Public License for more details.
+;;;
+;;; You should have received a copy of the GNU General Public License
+;;; along with GNU Guix.  If not, see <http://www.gnu.org/licenses/>.
+
+(define-module (gnu packages fpga)
+  #:use-module ((guix licenses) #:prefix license:)
+  #:use-module (guix packages)
+  #:use-module (guix download)
+  #:use-module (guix git-download)
+  #:use-module (guix build-system gnu)
+  #:use-module (guix build-system cmake)
+  #:use-module (gnu packages)
+  #:use-module (gnu packages pkg-config)
+  #:use-module (gnu packages tcl)
+  #:use-module (gnu packages readline)
+  #:use-module (gnu packages python)
+  #:use-module (gnu packages bison)
+  #:use-module (gnu packages flex)
+  #:use-module (gnu packages libffi)
+  #:use-module (gnu packages zip)
+  #:use-module (gnu packages perl)
+  #:use-module (gnu packages ghostscript)
+  #:use-module (gnu packages gawk)
+  #:use-module (gnu packages version-control)
+  #:use-module (gnu packages libftdi))
+
+(define-public abc
+ (let ((commit "5ae4b975c49c")
+       (revision "1"))
+  (package
+    (name "abc")
+    (version (string-append "0.0-" revision "-" (string-take commit 9)))
+    (source (origin
+              (method url-fetch)
+              (uri
+               (string-append "https://bitbucket.org/alanmi/abc/get/" commit ".zip"))
+              (file-name (string-append name "-" version "-checkout.zip"))
+              (sha256
+                (base32
+                   "1syygi1x40rdryih3galr4q8yg1w5bvdzl75hd27v1xq0l5bz3d0"))))
+    (build-system gnu-build-system)
+    (native-inputs
+     `(("unzip" ,unzip)))
+    (inputs
+     `(("readline" ,readline)))
+    (arguments
+     `(#:tests? #f ; no check target
+       #:phases
+       (modify-phases %standard-phases
+         (delete 'configure)
+         (replace 'install
+           (lambda* (#:key outputs #:allow-other-keys)
+             (let* ((out (assoc-ref outputs "out"))
+                    (out-bin (string-append out "/bin")))
+               (install-file "abc" out-bin)))))))
+    (home-page "http://people.eecs.berkeley.edu/~alanmi/abc/")
+    (synopsis "Sequential logic synthesis and formal verification")
+    (description "ABC is a program for sequential logic synthesis and
+formal verification.")
+    (license
+      (license:non-copyleft "https://fedoraproject.org/wiki/Licensing:MIT#Modern_Variants")))))

[PATCH v2 2/5] gnu: Add iverilog.

[Danny Milosavljevic]

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gnu: Add iverilog.

* gnu/packages/fpga.scm (iverilog): New variable.
---
 gnu/packages/fpga.scm | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)


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diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index f757a28..1d1c981 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -73,3 +73,38 @@
 formal verification.")
     (license
       (license:non-copyleft "https://fedoraproject.org/wiki/Licensing:MIT#Modern_Variants")))))
+
+(define-public iverilog
+  (package
+    (name "iverilog")
+    (version "10.1.1")
+    (source (origin
+              (method url-fetch)
+              (uri
+               (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/"
+                              "verilog-" version ".tar.gz"))
+              (sha256
+                (base32
+                   "1nnassxvq30rnn0r2p85rkb2zwxk97p109y13x3vr365wzgpbapx"))))
+    (build-system gnu-build-system)
+    (native-inputs
+     `(("flex" ,flex)
+       ("bison" ,bison)
+       ("ghostscript" ,ghostscript))) ; ps2pdf
+    (home-page "http://iverilog.icarus.com/")
+    (synopsis "FPGA Verilog simulation and synthesis tool")
+    (description "Icarus Verilog is a Verilog simulation and synthesis tool.
+It operates as a compiler, compiling source code written in Verilog
+(IEEE-1364) into some target format.
+For batch simulation, the compiler can generate an intermediate form
+called vvp assembly.
+This intermediate form is executed by the ``vvp'' command.
+For synthesis, the compiler generates netlists in the desired format.")
+    ;; GPL2 only because of:
+    ;; - ./driver/iverilog.man.in
+    ;; - ./iverilog-vpi.man.in
+    ;; - ./tgt-fpga/iverilog-fpga.man
+    ;; - ./vvp/vvp.man.in
+    ;; Otherwise would be GPL2+.
+    ;; You have to accept both GPL2 and LGPL2.1+.
+    (license (list license:gpl2 license:lgpl2.1+))))

[PATCH v2 3/5] gnu: Add yosys.

[Danny Milosavljevic]

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gnu: Add yosys.

* gnu/packages/fpga.scm (yosys): New variable.
---
 gnu/packages/fpga.scm | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)


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diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 1d1c981..763d746 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -108,3 +108,84 @@ For synthesis, the compiler generates netlists in the desired format.")
     ;; Otherwise would be GPL2+.
     ;; You have to accept both GPL2 and LGPL2.1+.
     (license (list license:gpl2 license:lgpl2.1+))))
+
+(define-public yosys
+  (package
+    (name "yosys")
+    (version "0.6")
+    (source (origin
+              (method url-fetch)
+              (uri
+               (string-append "https://github.com/cliffordwolf/yosys/archive/"
+                              name "-" version ".tar.gz"))
+              (sha256
+                (base32
+                   "02j0c0m9dfyjccynalf0aggj6gy20k7iphpkg5cn6sdirlkv8gmx"))
+              (file-name (string-append name "-" version "-checkout.tar.gz"))
+              (modules '((guix build utils)))
+              (snippet
+                '(substitute* "Makefile"
+                   (("ABCREV = .*") "ABCREV = default\n")))))
+    (build-system gnu-build-system)
+    (arguments
+     `(#:test-target "test"
+       #:make-flags (list "CC=gcc"
+                          "CXX=g++"
+                          (string-append "PREFIX=" %output))
+       #:phases
+       (modify-phases %standard-phases
+         (replace 'configure
+           (lambda* (#:key inputs (make-flags '()) #:allow-other-keys)
+             (zero? (apply system* "make" "config-gcc" make-flags))))
+         (add-after 'configure 'prepare-abc
+           (lambda* (#:key inputs #:allow-other-keys)
+             (let* ((sourceabc (assoc-ref inputs "abc"))
+                    (sourcebin (string-append sourceabc "/bin"))
+                    (source (string-append sourcebin "/abc")))
+                   (mkdir-p "abc")
+                   (call-with-output-file "abc/Makefile"
+                     (lambda (port)
+                       (format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
+                   (copy-file source "abc/abc")
+                   (zero? (system* "chmod" "+w" "abc/abc")))))
+          (add-before 'check 'fix-iverilog-references
+             (lambda* (#:key inputs native-inputs #:allow-other-keys)
+               (let* ((xinputs (or native-inputs inputs))
+                      (xdirname (assoc-ref xinputs "iverilog"))
+                      (iverilog (string-append xdirname "/bin/iverilog")))
+                     (substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
+                                    "./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
+                                    "./techlibs/ice40/tests/test_bram.sh"
+                                    "./techlibs/ice40/tests/test_ffs.sh"
+                                    "./techlibs/xilinx/tests/bram1.sh"
+                                    "./techlibs/xilinx/tests/bram2.sh"
+                                    "./tests/bram/run-single.sh"
+                                    "./tests/realmath/run-test.sh"
+                                    "./tests/simple/run-test.sh"
+                                    "./tests/techmap/mem_simple_4x1_runtest.sh"
+                                    "./tests/tools/autotest.sh"
+                                    "./tests/vloghtb/common.sh")
+                        (("if ! which iverilog") "if ! true")
+                        (("iverilog ") (string-append iverilog " "))
+                        (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
+                                                                iverilog
+                                                                "\"")))))))))
+    ;; TODO add xdot [patch the path to it here] as soon as I find out where it is.
+    (native-inputs
+     `(("pkg-config" ,pkg-config)
+       ("python" ,python)
+       ("bison" ,bison)
+       ("flex" ,flex)
+       ("gawk" , gawk) ; for the tests and "make" progress pretty-printing
+       ("tcl" ,tcl) ; tclsh for the tests
+       ("iverilog" ,iverilog) ; for the tests
+    ))
+    (inputs
+     `(("tcl" ,tcl)
+       ("readline" ,readline)
+       ("libffi" ,libffi)
+       ("abc" ,abc)))
+    (home-page "http://www.clifford.at/yosys/")
+    (synopsis "FPGA Verilog RTL synthesizer")
+    (description "Yosys synthesizes Verilog-2005.")
+    (license license:isc)))

[PATCH v2 4/5] gnu: Add icestorm.

[Danny Milosavljevic]

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gnu: Add icestorm.

* gnu/packages/fpga.scm (icestorm): New variable.
---
 gnu/packages/fpga.scm | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)


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diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 763d746..8c41cd3 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -189,3 +189,41 @@ For synthesis, the compiler generates netlists in the desired format.")
     (synopsis "FPGA Verilog RTL synthesizer")
     (description "Yosys synthesizes Verilog-2005.")
     (license license:isc)))
+
+(define-public icestorm
+  (let ((commit "12b2295c9087d94b75e374bb205ae4d76cf17e2f")
+        (revision "1"))
+   (package
+    (name "icestorm")
+    (version (string-append "0.0-" revision "-" (string-take commit 9)))
+    (source (origin
+              (method git-fetch)
+              (uri (git-reference
+                     (url "https://github.com/cliffordwolf/icestorm.git")
+                     (commit commit)))
+              (file-name (string-append name "-" version "-checkout"))
+              (sha256
+                (base32
+                   "1mmzlqvap6w8n4qzv3idvy51arkgn03692ssplwncy3akjrbsd2b"))))
+    (build-system gnu-build-system)
+    (arguments
+     `(#:tests? #f ; no unit tests that don't need an FPGA exist.
+       #:make-flags (list "CC=gcc" "CXX=g++"
+                          (string-append "PREFIX=" (assoc-ref %outputs "out")))
+       #:phases
+        (modify-phases %standard-phases
+          (add-after 'unpack 'remove-usr-local
+            (lambda _
+              (substitute* "iceprog/Makefile"
+                (("-L/usr/local/lib") ""))))
+          (delete 'configure))))
+    (inputs
+      `(("libftdi" ,libftdi)))
+    (native-inputs
+      `(("python-3" ,python)
+        ("pkg-config" ,pkg-config)))
+    (home-page "http://www.clifford.at/icestorm/")
+    (synopsis "Project IceStorm - Lattice iCE40 FPGAs bitstream tools")
+    (description "Project IceStorm - Lattice iCE40 FPGAs Bitstream Tools. 
+Includes the actual FTDI connector.")
+    (license license:isc))))

[PATCH v2 5/5] gnu: Add arachne-pnr.

[Danny Milosavljevic]

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gnu: Add arachne-pnr.

* gnu/packages/fpga.scm (arachne-pnr): New variable.
---
 gnu/packages/fpga.scm | 44 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)


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diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 8c41cd3..2d0d617 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -227,3 +227,47 @@ For synthesis, the compiler generates netlists in the desired format.")
     (description "Project IceStorm - Lattice iCE40 FPGAs Bitstream Tools. 
 Includes the actual FTDI connector.")
     (license license:isc))))
+
+(define-public arachne-pnr
+  (let ((commit "52e69ed207342710080d85c7c639480e74a021d7")
+        (revision "1"))
+   (package
+    (name "arachne-pnr")
+    (version (string-append "0.0-" revision "-" (string-take commit 9)))
+    (source (origin
+              (method git-fetch)
+              (uri (git-reference
+                     (url "https://github.com/cseed/arachne-pnr.git")
+                     (commit commit)))
+              (file-name (string-append name "-" version "-checkout"))
+              (sha256
+                (base32
+                   "15bdw5yxj76lxrwksp6liwmr6l1x77isf4bs50ys9rsnmiwh8c3w"))))
+    (build-system gnu-build-system)
+    (arguments
+     `(#:test-target "test"
+       #:phases (modify-phases %standard-phases
+       (replace 'configure
+         (lambda* (#:key outputs inputs #:allow-other-keys)
+           (substitute* '("Makefile")
+             (("DESTDIR = .*") (string-append "DESTDIR = "
+                                             (assoc-ref outputs "out")
+                                             "\n"))
+             (("ICEBOX = .*") (string-append "ICEBOX = "
+                                             (assoc-ref inputs "icestorm")
+                                             "/share/icebox\n")))
+           (substitute* '("./tests/fsm/generate.py"
+                          "./tests/combinatorial/generate.py")
+             (("#!/usr/bin/python") "#!/usr/bin/python2"))
+           #t)))))
+    (inputs
+     `(("icestorm" ,icestorm)))
+    (native-inputs
+     `(("git" ,git)  ; for determining its own version string
+       ("yosys" ,yosys) ; for tests
+       ("perl" ,perl) ; for shasum
+       ("python-2" ,python-2))) ; for tests
+    (home-page "https://github.com/cseed/arachne-pnr")
+    (synopsis "Place-and-Route tool for FPGAs")
+    (description "Arachne-PNR is a Place-and-Route Tool For FPGAs.")
+    (license license:gpl2))))

Re: [PATCH v2 0/5] Add FPGA Tools

[Danny Milosavljevic]

Ping. This is the newest version of the patch series that includes the changes you suggested.

Re: [PATCH v2 0/5] Add FPGA Tools

[Theodoros Foradis]

> This patch adds FPGA tools.

> Danny Milosavljevic (5):
>   gnu: Add abc.
>   gnu: Add iverilog.
>   gnu: Add yosys.
>   gnu: Add icestorm.
>   gnu: Add arachne-pnr.

>  gnu/local.mk          |   1 +
>  gnu/packages/fpga.scm | 273 ++++++++++++++++++++++++++++++++++++++++++++=
> ++++++
>  2 files changed, 274 insertions(+)
>  create mode 100644 gnu/packages/fpga.scm

Hello,

In order for icestorm to build, I had to add libusb to its inputs.

The toolchain was tested with an fpga. It's producing the bitstream, and
iceprog works as well. Iverilog is performing simulation as it should.

It's safe to say the patches can be pushed upstream, with the
modification to icestorm's inputs.

It would be helpful if we (I?) package gtkwave as well, so that one can view the waveforms
from the verilog simulations.
-- 
Theodoros Foradis

Re: [PATCH v2 0/5] Add FPGA Tools

[Danny Milosavljevic]

Hi,

thanks for testing this!

> In order for icestorm to build, I had to add libusb to its inputs.

I posted a patch "gnu: Move libusb from inputs to propagated-inputs" back in August which would fix that (by fixing libftdi). Adding libusb here is not the right fix.

> The toolchain was tested with an fpga. It's producing the bitstream, and
> iceprog works as well. Iverilog is performing simulation as it should.

Nice :)

> It would be helpful if we (I?) package gtkwave as well, so that one can view the waveforms
> from the verilog simulations.

Yeah...

Re: [PATCH v2 0/5] Add FPGA Tools

[Theodoros Foradis]

Hi,

> I posted a patch "gnu: Move libusb from inputs to propagated-inputs" back in August which would fix that (by fixing libftdi). Adding libusb here is not the right fix.

Are there any issues blocking that patch? Seems straightforward to me.

-- 
Theodoros Foradis

Re: [PATCH v2 0/5] Add FPGA Tools

[Danny Milosavljevic]

On Mon, 26 Sep 2016 13:53:24 +0300
Theodoros Foradis <theodoros.for@openmailbox.org> wrote:
> > I posted a patch "gnu: Move libusb from inputs to propagated-inputs" back in August which would fix that (by fixing libftdi). Adding libusb here is not the right fix.  
> 
> Are there any issues blocking that patch? Seems straightforward to me.

Yes, Andreas Enge told me to add a comment why I propagate. I did so now and posted the new patch. Let's see.

Re: [PATCH v2 0/5] Add FPGA Tools

[Theodoros Foradis]

> +       #:phases
> +        (modify-phases %standard-phases
> +          (add-after 'unpack 'remove-usr-local
> +            (lambda _
> +              (substitute* "iceprog/Makefile"
> +                (("-L/usr/local/lib") ""))))
> +          (delete 'configure))))

I made an omission in in my last mail.

The icestorm package builds as it is (with libusb added to the
inputs).But in order to ensure that the headers in /usr/local/include
are not used when building, the code above should be changed to:

(lambda _
  (substitute* "iceprog/Makefile"
    (("-L/usr/local/lib") "")
    (("-I/usr/local/include") ""))))
-- 
Theodoros Foradis

Re: [PATCH v2 0/5] Add FPGA Tools

[Danny Milosavljevic]

Hi,

> The icestorm package builds as it is (with libusb added to the
> inputs).But in order to ensure that the headers in /usr/local/include
> are not used when building, the code above should be changed to:
> 
> (lambda _
>   (substitute* "iceprog/Makefile"
>     (("-L/usr/local/lib") "")
>     (("-I/usr/local/include") ""))))

Good catch! I'm using GuixSD so there's nothing to use at /usr/local - I didn't notice.

Re: [PATCH v2 0/5] Add FPGA Tools

[Ludovic Courtès]

Theodoros Foradis <theodoros.for@openmailbox.org> skribis:

>> +       #:phases
>> +        (modify-phases %standard-phases
>> +          (add-after 'unpack 'remove-usr-local
>> +            (lambda _
>> +              (substitute* "iceprog/Makefile"
>> +                (("-L/usr/local/lib") ""))))
>> +          (delete 'configure))))
>
> I made an omission in in my last mail.
>
> The icestorm package builds as it is (with libusb added to the
> inputs).But in order to ensure that the headers in /usr/local/include
> are not used when building, the code above should be changed to:
>
> (lambda _
>   (substitute* "iceprog/Makefile"
>     (("-L/usr/local/lib") "")
>     (("-I/usr/local/include") ""))))

This is unnecessary unless you’re running “guix-daemon
--disable-chroot”, in which case many things break along these lines
anyway.

Ludo’.