From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6vUj-0006XO-IK for guix-patches@gnu.org; Mon, 01 Oct 2018 06:32:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g6vUg-00049C-Fj for guix-patches@gnu.org; Mon, 01 Oct 2018 06:32:05 -0400 Received: from debbugs.gnu.org ([208.118.235.43]:56482) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g6vUg-000491-6M for guix-patches@gnu.org; Mon, 01 Oct 2018 06:32:02 -0400 Received: from Debian-debbugs by debbugs.gnu.org with local (Exim 4.84_2) (envelope-from ) id 1g6vUf-0000nd-SI for guix-patches@gnu.org; Mon, 01 Oct 2018 06:32:01 -0400 Subject: [bug#32890] [PATCH 1/2] gnu: Add memtest86+. Resent-Message-ID: References: <874le6c6te.fsf@tobias.gr> <20181001101925.22883-1-me@tobias.gr> From: Tobias Geerinckx-Rice In-reply-to: <20181001101925.22883-1-me@tobias.gr> Date: Mon, 01 Oct 2018 12:31:43 +0200 Message-ID: <871s9ac60g.fsf@tobias.gr> MIME-Version: 1.0 Content-Type: text/plain; format=flowed List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: guix-patches-bounces+kyle=kyleam.com@gnu.org Sender: "Guix-patches" To: 32890@debbugs.gnu.org Tobias Geerinckx-Rice wrote: > (define-public msr-tools > (package > (name "msr-tools") > @@ -89,6 +151,7 @@ calibrated, and restored when the calibration > is applied.") > (arguments > `(#:make-flags > (list (string-append "sbindir=" (assoc-ref %outputs > "out") "/sbin")) > + #:tests? #f ; no test suite > #:phases > (modify-phases %standard-phases > (delete 'configure) ; no configure script > @@ -98,8 +161,7 @@ calibrated, and restored when the calibration > is applied.") > (let* ((out (assoc-ref outputs "out")) > (sbin (string-append out "/sbin"))) > (mkdir-p sbin) > - #t)))) > - #:tests? #f)) ; no test suite > + #t)))))) > (native-inputs > `(("unzip" ,unzip))) > ;; These registers and the CPUID instruction only exist on > (most) x86 chips. Have some cruft. Shouldn't affect the build, of course. Kind regards, T G-R