* [bug#43852] [PATCH] gnu: Add riscv-openocd.
@ 2020-10-07 20:02 Malte Frank Gerdes
2020-10-09 19:02 ` Andreas Enge
0 siblings, 1 reply; 4+ messages in thread
From: Malte Frank Gerdes @ 2020-10-07 20:02 UTC (permalink / raw)
To: 43852
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Hi,
this adds OpenOCD with RISC-V support to Guix.
There is a problem though: riscv-openocd bundles libjaylink, which is
also available as a package. The available package cannot be used
because it is too old and riscv-openocd has riscv-specific additions
made to it. So the question is: does this justify using the bundled
library or should I do something? (if yes, what?)
I have successfully used the package to communicate via JTAG with a
Sipeed Nano and a JLink V8.
I built this package successfully on: x86_64-linux, aarch64-linux
Malte
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From ccbb612dcf87e2e628febfee74f893726b6ca309 Mon Sep 17 00:00:00 2001
From: Malte Frank Gerdes <malte.f.gerdes@gmail.com>
Date: Wed, 7 Oct 2020 20:27:51 +0200
Subject: [PATCH] gnu: Add riscv-openocd.
* gnu/packages/embedded.scm (riscv-openocd): New variable.
* gnu/packages/patches/riscv-openocd-reproducibility.patch: New file.
* gnu/local.mk (dist_patch_DATA): Register patch.
---
gnu/local.mk | 2 +
gnu/packages/embedded.scm | 80 +++++++++++++++++++
.../riscv-openocd-reproducibility.patch | 57 +++++++++++++
3 files changed, 139 insertions(+)
create mode 100644 gnu/packages/patches/riscv-openocd-reproducibility.patch
diff --git a/gnu/local.mk b/gnu/local.mk
index f3b5b17e84..4fa460d4a1 100644
--- a/gnu/local.mk
+++ b/gnu/local.mk
@@ -37,6 +37,7 @@
# Copyright © 2020 Brice Waegeneire <brice@waegenei.re>
# Copyright © 2020 Tanguy Le Carrour <tanguy@bioneland.org>
# Copyright © 2020 Martin Becze <mjbecze@riseup.net>
+# Copyright © 2020 Malte Frank Gerdes <malte.f.gerdes@gmail.com>
#
# This file is part of GNU Guix.
#
@@ -1407,6 +1408,7 @@ dist_patch_DATA = \
%D%/packages/patches/pango-skip-libthai-test.patch \
%D%/packages/patches/pciutils-hurd-configure.patch \
%D%/packages/patches/ppsspp-disable-upgrade-and-gold.patch \
+ %D%/packages/patches/riscv-openocd-reproducibility.patch \
%D%/packages/patches/samba-fix-fcntl-hint-detection.patch \
%D%/packages/patches/sdl-pango-api_additions.patch \
%D%/packages/patches/sdl-pango-blit_overflow.patch \
diff --git a/gnu/packages/embedded.scm b/gnu/packages/embedded.scm
index f9f0e04238..89fdf81349 100644
--- a/gnu/packages/embedded.scm
+++ b/gnu/packages/embedded.scm
@@ -7,6 +7,7 @@
;;; Copyright © 2018, 2019 Clément Lassieur <clement@lassieur.org>
;;; Copyright © 2020 Marius Bakke <mbakke@fastmail.com>
;;; Copyright © 2020 Björn Höfling <bjoern.hoefling@bjoernhoefling.de>
+;;; Copyright © 2020 Malte Frank Gerdes <malte.f.gerdes@gmail.com>
;;;
;;; This file is part of GNU Guix.
;;;
@@ -38,6 +39,7 @@
#:use-module (gnu packages)
#:use-module (gnu packages autotools)
#:use-module ((gnu packages base) #:prefix base:)
+ #:use-module (gnu packages bash)
#:use-module (gnu packages bison)
#:use-module (gnu packages cross-base)
#:use-module (gnu packages dejagnu)
@@ -54,6 +56,7 @@
#:use-module (gnu packages python-xyz)
#:use-module (gnu packages swig)
#:use-module (gnu packages texinfo)
+ #:use-module (gnu packages version-control)
#:use-module (gnu packages xorg)
#:use-module (srfi srfi-1))
@@ -580,6 +583,83 @@ language.")
with a layered architecture of JTAG interface and TAP support.")
(license license:gpl2+)))
+(define-public riscv-openocd
+ (let ((commit "675259382bacade0d4cc44d1944be2aa6a893adc")
+ (revision "0"))
+ (package
+ (name "riscv-openocd")
+ (version (string-append "0.10.0-" revision "."
+ (string-take commit 7)))
+ (source (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://github.com/riscv/riscv-openocd")
+ (commit commit)))
+ (sha256
+ (base32
+ "083xyx2dq2f9yfkjpl8gm0icn96im1kip479y85nxl0z9ih7fxbf"))
+ (patches
+ (search-patches "riscv-openocd-reproducibility.patch"))))
+ (build-system gnu-build-system)
+ (native-inputs
+ `(("autoconf" ,autoconf)
+ ("automake" ,automake)
+ ("which" ,base:which)
+ ("libtool" ,libtool)
+ ("pkg-config" ,pkg-config)
+ ("bash-minimal" ,bash-minimal)
+ ("texinfo" ,texinfo)))
+ (inputs
+ `(("hidapi" ,hidapi)
+ ("jimtcl" ,jimtcl)
+ ("libftdi" ,libftdi)
+ ("libusb-compat" ,libusb-compat)))
+ (arguments
+ '(#:configure-flags
+ (append (list "--disable-werror"
+ "--enable-sysfsgpio"
+ "--disable-internal-jimtcl")
+ (map (lambda (programmer)
+ (string-append "--enable-" programmer))
+ '("amtjtagaccel" "armjtagew" "buspirate" "ftdi"
+ "gw16012" "jlink" "opendous" "osbdm"
+ "parport" "aice" "cmsis-dap" "dummy" "jtag_vpi"
+ "remote-bitbang" "rlink" "stlink" "ti-icdi" "ulink"
+ "usbprog" "vsllink" "usb-blaster-2" "usb_blaster"
+ "presto" "openjtag")))
+ #:phases
+ (modify-phases %standard-phases
+ (replace 'bootstrap
+ (lambda _
+ (chmod "src/jtag/drivers/libjaylink/autogen.sh" #o644)
+ (invoke "sh" "bootstrap" "nosubmodule")))
+ (add-after 'bootstrap 'bootstrap-jaylink
+ ;; we are using the bundled libjaylink here, because the original
+ ;; repo (https://git.zapb.de/libjaylink.git) is now behind a login
+ ;; and cannot be cloned anymore. This package has custom additions
+ ;; to libjaylink.
+ (lambda _
+ (with-directory-excursion "src/jtag/drivers/libjaylink"
+ (patch-shebang "autogen.sh")
+ (invoke "sh" "autogen.sh"))))
+ (add-before 'configure 'change-udev-group
+ (lambda _
+ (substitute* "contrib/60-openocd.rules"
+ (("plugdev") "dialout"))
+ #t))
+ (add-after 'install 'install-udev-rules
+ (lambda* (#:key outputs #:allow-other-keys)
+ (install-file "contrib/60-openocd.rules"
+ (string-append
+ (assoc-ref outputs "out")
+ "/lib/udev/rules.d/"))
+ #t)))))
+ (home-page "http://openocd.org")
+ (synopsis "On-Chip Debugger with RISC-V Support.")
+ (description "OpenOCD provides on-chip programming and debugging support
+with a layered architecture of JTAG interface and TAP support.")
+ (license license:gpl2+))))
+
;; The commits for all propeller tools are the stable versions published at
;; https://github.com/propellerinc/propgcc in the release_1_0. According to
;; personal correspondence with the developers in July 2017, more recent
diff --git a/gnu/packages/patches/riscv-openocd-reproducibility.patch b/gnu/packages/patches/riscv-openocd-reproducibility.patch
new file mode 100644
index 0000000000..3f7227e7a3
--- /dev/null
+++ b/gnu/packages/patches/riscv-openocd-reproducibility.patch
@@ -0,0 +1,57 @@
+diff --git a/Makefile.am b/Makefile.am
+index fcfd554c2..55088fef8 100644
+--- a/Makefile.am
++++ b/Makefile.am
+@@ -94,9 +94,7 @@ TCL_FILES = find $(srcdir)/$(TCL_PATH) -name '*.cfg' -o -name '*.tcl' -o -name '
+ sed -e 's,^$(srcdir)/$(TCL_PATH),,'
+
+ dist-hook:
+- if test -d $(srcdir)/.git -a \( ! -e $(distdir)/ChangeLog -o -w $(distdir)/ChangeLog \) ; then \
+- git --git-dir $(srcdir)/.git log | $(srcdir)/tools/git2cl/git2cl > $(distdir)/ChangeLog ; \
+- fi
++
+ for i in $$($(TCL_FILES)); do \
+ j="$(distdir)/$(TCL_PATH)/$$i" && \
+ mkdir -p "$$(dirname $$j)" && \
+@@ -122,7 +120,7 @@ distclean-local:
+ # instead we have a hook that enforces this in each workspace. To make sure
+ # that users actually use those hooks, we point git at them here.
+ all-local:
+- cd $(srcdir) && git config core.hooksPath ./git-hooks
++ echo "no git"
+
+ DISTCLEANFILES = doxygen.log
+
+diff --git a/doc/Makefile.am b/doc/Makefile.am
+index 67592038d..3a2e86049 100644
+--- a/doc/Makefile.am
++++ b/doc/Makefile.am
+@@ -4,8 +4,3 @@ info_TEXINFOS += %D%/openocd.texi
+ dist_man_MANS += %D%/openocd.1
+
+ EXTRA_DIST += %D%/manual
+-
+-MAINTAINERCLEANFILES += \
+- %D%/mdate-sh \
+- %D%/stamp-vti \
+- %D%/version.texi
+diff --git a/src/Makefile.am b/src/Makefile.am
+index 07981aa67..98e0c98c1 100644
+--- a/src/Makefile.am
++++ b/src/Makefile.am
+@@ -22,14 +22,9 @@ endif
+
+ # banner output includes RELSTR appended to $VERSION from the configure script
+ # guess-rev.sh returns either a repository version ID or "-snapshot"
+-if RELEASE
+ %C%_libopenocd_la_CPPFLAGS += -DRELSTR=\"\"
+ %C%_libopenocd_la_CPPFLAGS += -DGITVERSION=\"\"
+-else
+-%C%_libopenocd_la_CPPFLAGS += -DRELSTR=\"`$(top_srcdir)/guess-rev.sh $(top_srcdir)`\"
+-%C%_libopenocd_la_CPPFLAGS += -DGITVERSION=\"`cd $(top_srcdir) && git describe`\"
+-%C%_libopenocd_la_CPPFLAGS += -DPKGBLDDATE=\"`date +%F-%R`\"
+-endif
++
+
+ # add default CPPFLAGS
+ %C%_libopenocd_la_CPPFLAGS += $(AM_CPPFLAGS) $(CPPFLAGS)
--
2.28.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [bug#43852] [PATCH] gnu: Add riscv-openocd.
2020-10-07 20:02 [bug#43852] [PATCH] gnu: Add riscv-openocd Malte Frank Gerdes
@ 2020-10-09 19:02 ` Andreas Enge
2020-10-10 14:02 ` [bug#43852] [PATCH v2] " Malte Frank Gerdes
0 siblings, 1 reply; 4+ messages in thread
From: Andreas Enge @ 2020-10-09 19:02 UTC (permalink / raw)
To: Malte Frank Gerdes; +Cc: 43852
Hello,
since I am speaking as someone who does not know what these packages are
about, please take what follows with a grain of salt.
On Wed, Oct 07, 2020 at 10:02:09PM +0200, Malte Frank Gerdes wrote:
> libjaylink ... is
> ... available as a package. The available package ...
> ... is too old ...
> ... should I do something?
Written like this, I would say you could try updating it, independently
of your target package. Then the question is whether you break anything
else:
guix refresh -l libjaylink
A single dependent package: openocd@0.10.0
So there already is an openocd, which maybe should be updated at the same
time?
And do you really need a new package, or could it be enough to provide
more inputs or configuration flags to the existing one? Otherwise, how
about inheriting? The name also is weird, see the section in the manual;
we normally keep the upstream project name.
Andreas
^ permalink raw reply [flat|nested] 4+ messages in thread
* [bug#43852] [PATCH v2] gnu: Add riscv-openocd.
2020-10-09 19:02 ` Andreas Enge
@ 2020-10-10 14:02 ` Malte Frank Gerdes
2020-10-22 14:49 ` bug#43852: " Ludovic Courtès
0 siblings, 1 reply; 4+ messages in thread
From: Malte Frank Gerdes @ 2020-10-10 14:02 UTC (permalink / raw)
To: Andreas Enge; +Cc: 43852
[-- Attachment #1: Type: text/plain, Size: 1544 bytes --]
Andreas Enge <andreas@enge.fr> writes:
> Hello,
>
> since I am speaking as someone who does not know what these packages are
> about, please take what follows with a grain of salt.
Feedback is always good! especially when it leads to realizing how it
should actually be done.
> On Wed, Oct 07, 2020 at 10:02:09PM +0200, Malte Frank Gerdes wrote:
>> libjaylink ... is
>> ... available as a package. The available package ...
>> ... is too old ...
>> ... should I do something?
>
> Written like this, I would say you could try updating it, independently
> of your target package. Then the question is whether you break anything
> else:
> guix refresh -l libjaylink
> A single dependent package: openocd@0.10.0
>
> So there already is an openocd, which maybe should be updated at the same
> time?
The problem was: i didn't realize that libjaylink has a new release and
that it's actually possible to clone it; because the official upstream
repo seems to be locked behind a login. But there is a mirror of it on
repo.or.cz - which i'm now using.
> And do you really need a new package, or could it be enough to provide
> more inputs or configuration flags to the existing one? Otherwise, how
> about inheriting? The name also is weird, see the section in the manual;
> we normally keep the upstream project name.
I used riscv/riscv-openocd as the upstream repo (github), but it seems
that this isn't necessary. So i'm now just updating the package we
already have. It doesn't have a new release, so i had to use the git
master.
Malte
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From 5be71d32e9694fadea411a267e36333697510bb1 Mon Sep 17 00:00:00 2001
From: Malte Frank Gerdes <malte.f.gerdes@gmail.com>
Date: Sat, 10 Oct 2020 15:24:46 +0200
Subject: [PATCH 1/2] gnu: libjaylink: Update to 0.2.0
* gnu/packages/embedded.scm (libjaylink): Update to 0.2.0
[origin]: Substitute upstream repository location.
---
gnu/packages/embedded.scm | 52 ++++++++++++++++++---------------------
1 file changed, 24 insertions(+), 28 deletions(-)
diff --git a/gnu/packages/embedded.scm b/gnu/packages/embedded.scm
index f9f0e04238..1eacb72a45 100644
--- a/gnu/packages/embedded.scm
+++ b/gnu/packages/embedded.scm
@@ -458,35 +458,31 @@ languages are C and C++.")
,@(package-arguments gdb)))))
(define-public libjaylink
- ;; No release tarballs available.
- (let ((commit "699b7001d34a79c8e7064503dde1bede786fd7f0")
- (revision "2"))
- (package
- (name "libjaylink")
- (version (string-append "0.1.0-" revision "."
- (string-take commit 7)))
- (source (origin
- (method git-fetch)
- (uri (git-reference
- (url "https://git.zapb.de/libjaylink.git")
- (commit commit)))
- (file-name (string-append name "-" version "-checkout"))
- (sha256
- (base32
- "034872d44myycnzn67v5b8ixrgmg8sk32aqalvm5x7108w2byww1"))))
- (build-system gnu-build-system)
- (native-inputs
- `(("autoconf" ,autoconf)
- ("automake" ,automake)
- ("libtool" ,libtool)
- ("pkg-config" ,pkg-config)))
- (inputs
- `(("libusb" ,libusb)))
- (home-page "https://repo.or.cz/w/libjaylink.git")
- (synopsis "Library to interface Segger J-Link devices")
- (description "libjaylink is a shared library written in C to access
+ (package
+ (name "libjaylink")
+ (version "0.2.0")
+ (source (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://repo.or.cz/libjaylink.git")
+ (commit version)))
+ (file-name (git-file-name name version))
+ (sha256
+ (base32
+ "0ndyfh51hiqyv2yscpj6qd091w7myxxjid3a6rx8f6k233vy826q"))))
+ (build-system gnu-build-system)
+ (native-inputs
+ `(("autoconf" ,autoconf)
+ ("automake" ,automake)
+ ("libtool" ,libtool)
+ ("pkg-config" ,pkg-config)))
+ (inputs
+ `(("libusb" ,libusb)))
+ (home-page "https://repo.or.cz/w/libjaylink.git")
+ (synopsis "Library to interface Segger J-Link devices")
+ (description "libjaylink is a shared library written in C to access
SEGGER J-Link and compatible devices.")
- (license license:gpl2+))))
+ (license license:gpl2+)))
(define-public jimtcl
(package
--
2.28.0
[-- Attachment #3: 0002-gnu-openocd-Update-to-9a877a83a1c8b1f105cdc0de46c5cb.patch --]
[-- Type: text/x-patch, Size: 33937 bytes --]
From de5299f976f54ef431e856ca15b045408495491b Mon Sep 17 00:00:00 2001
From: Malte Frank Gerdes <malte.f.gerdes@gmail.com>
Date: Sat, 10 Oct 2020 15:31:14 +0200
Subject: [PATCH 2/2] gnu: openocd: Update to
9a877a83a1c8b1f105cdc0de46c5cbc4d9e8799e.
* gnu/packages/embedded.scm (openocd): Update to 9a877a83a1c8b1f105cdc0de46c5cbc4d9e8799e.
[version]: Substitute release with current master.
[source]: Remove openocd-nrf52.patch
[arguments]: Replace bootstrap build phase.
* gnu/local.mk: Remove openocd-nrf52.patch.
* gnu/packages/patches/openocd-nrf52.patch: Remove file.
---
gnu/local.mk | 2 +-
gnu/packages/embedded.scm | 124 ++--
gnu/packages/patches/openocd-nrf52.patch | 827 -----------------------
3 files changed, 65 insertions(+), 888 deletions(-)
delete mode 100644 gnu/packages/patches/openocd-nrf52.patch
diff --git a/gnu/local.mk b/gnu/local.mk
index f3b5b17e84..70a563cf99 100644
--- a/gnu/local.mk
+++ b/gnu/local.mk
@@ -37,6 +37,7 @@
# Copyright © 2020 Brice Waegeneire <brice@waegenei.re>
# Copyright © 2020 Tanguy Le Carrour <tanguy@bioneland.org>
# Copyright © 2020 Martin Becze <mjbecze@riseup.net>
+# Copyright © 2020 Malte Frank Gerdes <mate.f.gerdes@gmail.com>
#
# This file is part of GNU Guix.
#
@@ -1385,7 +1386,6 @@ dist_patch_DATA = \
%D%/packages/patches/openfoam-4.1-cleanup.patch \
%D%/packages/patches/openjdk-10-idlj-reproducibility.patch \
%D%/packages/patches/openmpi-mtl-priorities.patch \
- %D%/packages/patches/openocd-nrf52.patch \
%D%/packages/patches/openssh-hurd.patch \
%D%/packages/patches/openresolv-restartcmd-guix.patch \
%D%/packages/patches/openscad-parser-boost-1.72.patch \
diff --git a/gnu/packages/embedded.scm b/gnu/packages/embedded.scm
index 1eacb72a45..cc26b17ea6 100644
--- a/gnu/packages/embedded.scm
+++ b/gnu/packages/embedded.scm
@@ -514,67 +514,71 @@ language.")
(license license:bsd-2)))
(define-public openocd
- (package
- (name "openocd")
- (version "0.10.0")
- (source (origin
- (method url-fetch)
- (uri (string-append "mirror://sourceforge/openocd/openocd/"
- version "/openocd-" version ".tar.gz"))
- (sha256
- (base32
- "09p57y3c2spqx4vjjlz1ljm1lcd0j9q8g76ywxqgn3yc34wv18zd"))
- ;; FIXME: Remove after nrf52 patch is merged.
- (patches
- (search-patches "openocd-nrf52.patch"))))
- (build-system gnu-build-system)
- (native-inputs
- `(("autoconf" ,autoconf)
- ("automake" ,automake)
- ("libtool" ,libtool)
- ("pkg-config" ,pkg-config)))
- (inputs
- `(("hidapi" ,hidapi)
- ("jimtcl" ,jimtcl)
- ("libftdi" ,libftdi)
- ("libjaylink" ,libjaylink)
- ("libusb-compat" ,libusb-compat)))
- (arguments
- '(#:configure-flags
- (append (list "--disable-werror"
- "--enable-sysfsgpio"
- "--disable-internal-jimtcl"
- "--disable-internal-libjaylink")
- (map (lambda (programmer)
- (string-append "--enable-" programmer))
- '("amtjtagaccel" "armjtagew" "buspirate" "ftdi"
- "gw16012" "jlink" "opendous" "osbdm"
- "parport" "aice" "cmsis-dap" "dummy" "jtag_vpi"
- "remote-bitbang" "rlink" "stlink" "ti-icdi" "ulink"
- "usbprog" "vsllink" "usb-blaster-2" "usb_blaster"
- "presto" "openjtag")))
- #:phases
- (modify-phases %standard-phases
- ;; Required because of patched sources.
- (add-before 'configure 'autoreconf
- (lambda _ (invoke "autoreconf" "-vfi") #t))
- (add-after 'autoreconf 'change-udev-group
- (lambda _
- (substitute* "contrib/60-openocd.rules"
- (("plugdev") "dialout"))
- #t))
- (add-after 'install 'install-udev-rules
- (lambda* (#:key outputs #:allow-other-keys)
- (install-file "contrib/60-openocd.rules"
- (string-append
- (assoc-ref outputs "out")
- "/lib/udev/rules.d/"))
- #t)))))
- (home-page "http://openocd.org")
- (synopsis "On-Chip Debugger")
- (description "OpenOCD provides on-chip programming and debugging support
+ (let ((commit "9a877a83a1c8b1f105cdc0de46c5cbc4d9e8799e")
+ (revision "0"))
+ (package
+ (name "openocd")
+ (version (string-append "0.10.0-" revision "."
+ (string-take commit 7)))
+ (source (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://git.code.sf.net/p/openocd/code")
+ (commit commit)))
+ (file-name (string-append name "-" version "-checkout"))
+ (sha256
+ (base32
+ "1q536cp80v2bcy6xwk08f1r2ljyw13jchx3a1z7d3ni3vqql7rc6"))))
+ (build-system gnu-build-system)
+ (native-inputs
+ `(("autoconf" ,autoconf)
+ ("automake" ,automake)
+ ("libtool" ,libtool)
+ ("which" ,base:which)
+ ("pkg-config" ,pkg-config)))
+ (inputs
+ `(("hidapi" ,hidapi)
+ ("jimtcl" ,jimtcl)
+ ("libftdi" ,libftdi)
+ ("libjaylink" ,libjaylink)
+ ("libusb-compat" ,libusb-compat)))
+ (arguments
+ '(#:configure-flags
+ (append (list "--disable-werror"
+ "--enable-sysfsgpio"
+ "--disable-internal-jimtcl"
+ "--disable-internal-libjaylink")
+ (map (lambda (programmer)
+ (string-append "--enable-" programmer))
+ '("amtjtagaccel" "armjtagew" "buspirate" "ftdi"
+ "gw16012" "jlink" "opendous" "osbdm"
+ "parport" "aice" "cmsis-dap" "dummy" "jtag_vpi"
+ "remote-bitbang" "rlink" "stlink" "ti-icdi" "ulink"
+ "usbprog" "vsllink" "usb-blaster-2" "usb_blaster"
+ "presto" "openjtag")))
+ #:phases
+ (modify-phases %standard-phases
+ (replace 'bootstrap
+ (lambda _
+ (patch-shebang "bootstrap")
+ (invoke "./bootstrap" "nosubmodule")))
+ (add-after 'autoreconf 'change-udev-group
+ (lambda _
+ (substitute* "contrib/60-openocd.rules"
+ (("plugdev") "dialout"))
+ #t))
+ (add-after 'install 'install-udev-rules
+ (lambda* (#:key outputs #:allow-other-keys)
+ (install-file "contrib/60-openocd.rules"
+ (string-append
+ (assoc-ref outputs "out")
+ "/lib/udev/rules.d/"))
+ #t)))))
+ (home-page "http://openocd.org")
+ (synopsis "On-Chip Debugger")
+ (description "OpenOCD provides on-chip programming and debugging support
with a layered architecture of JTAG interface and TAP support.")
- (license license:gpl2+)))
+ (license license:gpl2+))))
;; The commits for all propeller tools are the stable versions published at
;; https://github.com/propellerinc/propgcc in the release_1_0. According to
diff --git a/gnu/packages/patches/openocd-nrf52.patch b/gnu/packages/patches/openocd-nrf52.patch
deleted file mode 100644
index 0ec4348cb4..0000000000
--- a/gnu/packages/patches/openocd-nrf52.patch
+++ /dev/null
@@ -1,827 +0,0 @@
-This patch adds support for nRF52 series devices. It is patchset 7 from
-<http://openocd.zylin.com/#/c/3511/>, which has been tested, but not
-merged yet in master.
-
-From: Michael Dietz <mjdietzx@gmail.com>
-Date: Mon, 30 May 2016 12:50:44 +0000 (-0700)
-Subject: Added support for nRF52 Series Devices.
-X-Git-Url: http://openocd.zylin.com/gitweb?p=openocd.git;a=commitdiff_plain;h=9ba15633e221d9d72e320372ba8f49d3f30d4bce
-
-Added support for nRF52 Series Devices.
-
-Both nrf52.c and nrf52.cfg are based off of previous nRF51 files.
-- Some possible race conditions with NVMC have been fixed in nRF52.c
-- Removed nrf51_get_probed_chip_if_halted() as the core does not have to be halted to perform operations where it is called.
-- Only registers that are needed by openOCD are defined, some registers in nRF51 don't exist in nRF52 and are removed.
-- Some all around cleanup has been done.
-- The protection mechanism is completely different on nRF52 and this has not been implemented yet - just prints a warning and returns for now.
-
-Change-Id: I4dd42c86f33f450709bb981806c2655f04aa6201
-Signed-off-by: Michael Dietz <mjdietzx@gmail.com>
----
-
-diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
-index 727e4f2..839667c 100644
---- a/src/flash/nor/Makefile.am
-+++ b/src/flash/nor/Makefile.am
-@@ -36,6 +36,7 @@ NOR_DRIVERS = \
- %D%/niietcm4.c \
- %D%/non_cfi.c \
- %D%/nrf51.c \
-+ %D%/nrf52.c \
- %D%/numicro.c \
- %D%/ocl.c \
- %D%/pic32mx.c \
-diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
-index 56a5cb2..071273e 100644
---- a/src/flash/nor/drivers.c
-+++ b/src/flash/nor/drivers.c
-@@ -48,6 +48,7 @@ extern struct flash_driver mdr_flash;
- extern struct flash_driver mrvlqspi_flash;
- extern struct flash_driver niietcm4_flash;
- extern struct flash_driver nrf51_flash;
-+extern struct flash_driver nrf52_flash;
- extern struct flash_driver numicro_flash;
- extern struct flash_driver ocl_flash;
- extern struct flash_driver pic32mx_flash;
-@@ -100,6 +101,7 @@ static struct flash_driver *flash_drivers[] = {
- &mrvlqspi_flash,
- &niietcm4_flash,
- &nrf51_flash,
-+ &nrf52_flash,
- &numicro_flash,
- &ocl_flash,
- &pic32mx_flash,
-diff --git a/src/flash/nor/nrf52.c b/src/flash/nor/nrf52.c
-new file mode 100644
-index 0000000..7f2bd35
---- /dev/null
-+++ b/src/flash/nor/nrf52.c
-@@ -0,0 +1,733 @@
-+/***************************************************************************
-+ * Copyright (C) 2013 Synapse Product Development *
-+ * Andrey Smirnov <andrew.smironv@gmail.com> *
-+ * Angus Gratton <gus@projectgus.com> *
-+ * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
-+ * *
-+ * This program is free software; you can redistribute it and/or modify *
-+ * it under the terms of the GNU General Public License as published by *
-+ * the Free Software Foundation; either version 2 of the License, or *
-+ * (at your option) any later version. *
-+ * *
-+ * This program is distributed in the hope that it will be useful, *
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
-+ * GNU General Public License for more details. *
-+ * *
-+ * You should have received a copy of the GNU General Public License *
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
-+ ***************************************************************************/
-+
-+#ifdef HAVE_CONFIG_H
-+#include "config.h"
-+#endif
-+
-+#include <stdlib.h>
-+
-+#include "imp.h"
-+#include <target/algorithm.h>
-+#include <target/armv7m.h>
-+#include <helper/types.h>
-+
-+/* nRF52 Register addresses used by openOCD. */
-+#define NRF52_FLASH_BASE_ADDR (0x0)
-+
-+#define NRF52_FICR_BASE_ADDR (0x10000000)
-+#define NRF52_FICR_CODEPAGESIZE_ADDR (NRF52_FICR_BASE_ADDR | 0x010)
-+#define NRF52_FICR_CODESIZE_ADDR (NRF52_FICR_BASE_ADDR | 0x014)
-+
-+#define NRF52_UICR_BASE_ADDR (0x10001000)
-+
-+#define NRF52_NVMC_BASE_ADDR (0x4001E000)
-+#define NRF52_NVMC_READY_ADDR (NRF52_NVMC_BASE_ADDR | 0x400)
-+#define NRF52_NVMC_CONFIG_ADDR (NRF52_NVMC_BASE_ADDR | 0x504)
-+#define NRF52_NVMC_ERASEPAGE_ADDR (NRF52_NVMC_BASE_ADDR | 0x508)
-+#define NRF52_NVMC_ERASEALL_ADDR (NRF52_NVMC_BASE_ADDR | 0x50C)
-+#define NRF52_NVMC_ERASEUICR_ADDR (NRF52_NVMC_BASE_ADDR | 0x514)
-+
-+/* nRF52 bit fields. */
-+enum nrf52_nvmc_config_bits {
-+ NRF52_NVMC_CONFIG_REN = 0x0,
-+ NRF52_NVMC_CONFIG_WEN = 0x01,
-+ NRF52_NVMC_CONFIG_EEN = 0x02
-+};
-+
-+enum nrf52_nvmc_ready_bits {
-+ NRF52_NVMC_BUSY = 0x0,
-+ NRF52_NVMC_READY = 0x01
-+};
-+
-+/* nRF52 state information. */
-+struct nrf52_info {
-+ uint32_t code_page_size; /* Size of FLASH page in bytes. */
-+ uint32_t code_memory_size; /* Size of Code FLASH region in bytes. */
-+
-+ struct {
-+ bool probed;
-+ int (*write) (struct flash_bank *bank,
-+ struct nrf52_info *chip,
-+ const uint8_t *buffer, uint32_t offset, uint32_t count);
-+ } bank[2]; /* There are two regions in nRF52 FLASH - Code and UICR. */
-+ struct target *target;
-+};
-+
-+static int nrf52_protect_check(struct flash_bank *bank);
-+
-+static int nrf52_probe(struct flash_bank *bank)
-+{
-+ int res;
-+ struct nrf52_info *chip = bank->driver_priv;
-+ assert(chip != NULL);
-+
-+ res = target_read_u32(chip->target,
-+ NRF52_FICR_CODEPAGESIZE_ADDR,
-+ &chip->code_page_size);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Couldn't read code page size");
-+ return res;
-+ }
-+
-+ res = target_read_u32(chip->target,
-+ NRF52_FICR_CODESIZE_ADDR,
-+ &chip->code_memory_size);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Couldn't read code memory size");
-+ return res;
-+ }
-+
-+ chip->code_memory_size = chip->code_memory_size * chip->code_page_size;
-+
-+ if (bank->base == NRF52_FLASH_BASE_ADDR) {
-+ bank->size = chip->code_memory_size;
-+ bank->num_sectors = bank->size / chip->code_page_size;
-+ bank->sectors = calloc(bank->num_sectors,
-+ sizeof((bank->sectors)[0]));
-+ if (!bank->sectors)
-+ return ERROR_FLASH_BANK_NOT_PROBED;
-+
-+ /* Fill out the sector information: All nRF51 sectors are the same size. */
-+ for (int i = 0; i < bank->num_sectors; i++) {
-+ bank->sectors[i].size = chip->code_page_size;
-+ bank->sectors[i].offset = i * chip->code_page_size;
-+
-+ /* Mark as unknown. */
-+ bank->sectors[i].is_erased = -1;
-+ bank->sectors[i].is_protected = -1;
-+ }
-+
-+ nrf52_protect_check(bank);
-+
-+ chip->bank[0].probed = true;
-+ } else { /* This is the UICR bank. */
-+ bank->size = chip->code_page_size;
-+ bank->num_sectors = 1;
-+ bank->sectors = calloc(bank->num_sectors,
-+ sizeof((bank->sectors)[0]));
-+ if (!bank->sectors)
-+ return ERROR_FLASH_BANK_NOT_PROBED;
-+
-+ bank->sectors[0].size = bank->size;
-+ bank->sectors[0].offset = 0;
-+
-+ bank->sectors[0].is_erased = -1;
-+ bank->sectors[0].is_protected = -1;
-+
-+ chip->bank[1].probed = true;
-+ }
-+
-+ return ERROR_OK;
-+}
-+
-+static int nrf52_bank_is_probed(struct flash_bank *bank)
-+{
-+ struct nrf52_info *chip = bank->driver_priv;
-+ assert(chip != NULL);
-+
-+ return chip->bank[bank->bank_number].probed;
-+}
-+
-+static int nrf52_auto_probe(struct flash_bank *bank)
-+{
-+ if (!nrf52_bank_is_probed(bank))
-+ return nrf52_probe(bank);
-+ else
-+ return ERROR_OK;
-+}
-+
-+static int nrf52_wait_for_nvmc(struct nrf52_info *chip)
-+{
-+ int res;
-+ uint32_t ready;
-+ int timeout = 100;
-+
-+ do {
-+ res = target_read_u32(chip->target, NRF52_NVMC_READY_ADDR, &ready);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Couldn't read NVMC_READY register");
-+ return res;
-+ }
-+
-+ if (ready == NRF52_NVMC_READY)
-+ return ERROR_OK;
-+
-+ alive_sleep(1);
-+ } while (timeout--);
-+
-+ LOG_DEBUG("Timed out waiting for the NVMC to be ready");
-+ return ERROR_FLASH_BUSY;
-+}
-+
-+static int nrf52_nvmc_erase_enable(struct nrf52_info *chip)
-+{
-+ int res;
-+
-+ res = nrf52_wait_for_nvmc(chip);
-+ if (res != ERROR_OK)
-+ return res;
-+
-+ res = target_write_u32(chip->target,
-+ NRF52_NVMC_CONFIG_ADDR,
-+ NRF52_NVMC_CONFIG_EEN);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Failed to configure the NVMC for erasing");
-+ return res;
-+ }
-+
-+ return res;
-+}
-+
-+static int nrf52_nvmc_write_enable(struct nrf52_info *chip)
-+{
-+ int res;
-+
-+ res = nrf52_wait_for_nvmc(chip);
-+ if (res != ERROR_OK)
-+ return res;
-+
-+ res = target_write_u32(chip->target,
-+ NRF52_NVMC_CONFIG_ADDR,
-+ NRF52_NVMC_CONFIG_WEN);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Failed to configure the NVMC for writing");
-+ return res;
-+ }
-+
-+ return res;
-+}
-+
-+static int nrf52_nvmc_read_only(struct nrf52_info *chip)
-+{
-+ int res;
-+
-+ res = nrf52_wait_for_nvmc(chip);
-+ if (res != ERROR_OK)
-+ return res;
-+
-+ res = target_write_u32(chip->target,
-+ NRF52_NVMC_CONFIG_ADDR,
-+ NRF52_NVMC_CONFIG_REN);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Failed to configure the NVMC for read-only");
-+ return res;
-+ }
-+
-+ return res;
-+}
-+
-+static int nrf52_nvmc_generic_erase(struct nrf52_info *chip,
-+ uint32_t erase_register,
-+ uint32_t erase_value)
-+{
-+ int res;
-+
-+ res = nrf52_nvmc_erase_enable(chip);
-+ if (res != ERROR_OK)
-+ return res;
-+
-+ res = target_write_u32(chip->target,
-+ erase_register,
-+ erase_value);
-+ if (res != ERROR_OK)
-+ LOG_ERROR("Failed to write NVMC erase register");
-+
-+ return nrf52_nvmc_read_only(chip);
-+}
-+
-+static int nrf52_protect_check(struct flash_bank *bank)
-+{
-+ LOG_WARNING("nrf52_protect_check() is not implemented for nRF52 series devices yet");
-+ return ERROR_OK;
-+}
-+
-+static int nrf52_protect(struct flash_bank *bank, int set, int first, int last)
-+{
-+ LOG_WARNING("nrf52_protect() is not implemented for nRF52 series devices yet");
-+ return ERROR_OK;
-+}
-+
-+static struct flash_sector *nrf52_find_sector_by_address(struct flash_bank *bank, uint32_t address)
-+{
-+ struct nrf52_info *chip = bank->driver_priv;
-+ assert(chip != NULL);
-+
-+ for (int i = 0; i < bank->num_sectors; i++)
-+ if (bank->sectors[i].offset <= address &&
-+ address < (bank->sectors[i].offset + chip->code_page_size)) {
-+ return &bank->sectors[i];
-+ }
-+
-+ return NULL;
-+}
-+
-+static int nrf52_erase_all(struct nrf52_info *chip)
-+{
-+ LOG_DEBUG("Erasing all non-volatile memory");
-+ return nrf52_nvmc_generic_erase(chip,
-+ NRF52_NVMC_ERASEALL_ADDR,
-+ 0x01);
-+}
-+
-+static int nrf52_erase_page(struct flash_bank *bank,
-+ struct nrf52_info *chip,
-+ struct flash_sector *sector)
-+{
-+ int res;
-+
-+ LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
-+ if (sector->is_protected == 1) {
-+ LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset);
-+ return ERROR_FAIL;
-+ }
-+
-+ if (bank->base == NRF52_UICR_BASE_ADDR) {
-+ res = nrf52_nvmc_generic_erase(chip,
-+ NRF52_NVMC_ERASEUICR_ADDR,
-+ 0x00000001);
-+ } else {
-+ res = nrf52_nvmc_generic_erase(chip,
-+ NRF52_NVMC_ERASEPAGE_ADDR,
-+ sector->offset);
-+ }
-+
-+ if (res == ERROR_OK)
-+ sector->is_erased = 1;
-+ return res;
-+}
-+
-+static const uint8_t nrf52_flash_write_code[] = {
-+ /* See contrib/loaders/flash/cortex-m0.S */
-+ /* <wait_fifo>: */
-+ 0x0d, 0x68, /* ldr r5, [r1, #0] */
-+ 0x00, 0x2d, /* cmp r5, #0 */
-+ 0x0b, 0xd0, /* beq.n 1e <exit> */
-+ 0x4c, 0x68, /* ldr r4, [r1, #4] */
-+ 0xac, 0x42, /* cmp r4, r5 */
-+ 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
-+ 0x20, 0xcc, /* ldmia r4!, {r5} */
-+ 0x20, 0xc3, /* stmia r3!, {r5} */
-+ 0x94, 0x42, /* cmp r4, r2 */
-+ 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
-+ 0x0c, 0x46, /* mov r4, r1 */
-+ 0x08, 0x34, /* adds r4, #8 */
-+ /* <no_wrap>: */
-+ 0x4c, 0x60, /* str r4, [r1, #4] */
-+ 0x04, 0x38, /* subs r0, #4 */
-+ 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
-+ /* <exit>: */
-+ 0x00, 0xbe /* bkpt 0x0000 */
-+};
-+
-+
-+/* Start a low level flash write for the specified region */
-+static int nrf52_ll_flash_write(struct nrf52_info *chip, uint32_t offset, const uint8_t *buffer, uint32_t bytes)
-+{
-+ struct target *target = chip->target;
-+ uint32_t buffer_size = 8192;
-+ struct working_area *write_algorithm;
-+ struct working_area *source;
-+ uint32_t address = NRF52_FLASH_BASE_ADDR + offset;
-+ struct reg_param reg_params[4];
-+ struct armv7m_algorithm armv7m_info;
-+ int retval = ERROR_OK;
-+
-+ LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32" bytes=0x%"PRIx32, offset, bytes);
-+ assert(bytes % 4 == 0);
-+
-+ /* allocate working area with flash programming code */
-+ if (target_alloc_working_area(target, sizeof(nrf52_flash_write_code),
-+ &write_algorithm) != ERROR_OK) {
-+ LOG_WARNING("no working area available, falling back to slow memory writes");
-+
-+ for (; bytes > 0; bytes -= 4) {
-+ retval = target_write_memory(chip->target,
-+ offset, 4, 1, buffer);
-+ if (retval != ERROR_OK)
-+ return retval;
-+
-+ retval = nrf52_wait_for_nvmc(chip);
-+ if (retval != ERROR_OK)
-+ return retval;
-+
-+ offset += 4;
-+ buffer += 4;
-+ }
-+
-+ return ERROR_OK;
-+ }
-+
-+ LOG_WARNING("using fast async flash loader. This is currently supported");
-+ LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
-+ LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf52.cfg to disable it");
-+
-+ retval = target_write_buffer(target, write_algorithm->address,
-+ sizeof(nrf52_flash_write_code),
-+ nrf52_flash_write_code);
-+ if (retval != ERROR_OK)
-+ return retval;
-+
-+ /* memory buffer */
-+ while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
-+ buffer_size /= 2;
-+ buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
-+ if (buffer_size <= 256) {
-+ /* free working area, write algorithm already allocated */
-+ target_free_working_area(target, write_algorithm);
-+
-+ LOG_WARNING("No large enough working area available, can't do block memory writes");
-+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-+ }
-+ }
-+
-+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
-+ armv7m_info.core_mode = ARM_MODE_THREAD;
-+
-+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
-+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer start */
-+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer end */
-+ init_reg_param(®_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
-+
-+ buf_set_u32(reg_params[0].value, 0, 32, bytes);
-+ buf_set_u32(reg_params[1].value, 0, 32, source->address);
-+ buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
-+ buf_set_u32(reg_params[3].value, 0, 32, address);
-+
-+ retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
-+ 0, NULL,
-+ 4, reg_params,
-+ source->address, source->size,
-+ write_algorithm->address, 0,
-+ &armv7m_info);
-+
-+ target_free_working_area(target, source);
-+ target_free_working_area(target, write_algorithm);
-+
-+ destroy_reg_param(®_params[0]);
-+ destroy_reg_param(®_params[1]);
-+ destroy_reg_param(®_params[2]);
-+ destroy_reg_param(®_params[3]);
-+
-+ return retval;
-+}
-+
-+/* Check and erase flash sectors in specified range, then start a low level page write.
-+ start/end must be sector aligned.
-+*/
-+static int nrf52_write_pages(struct flash_bank *bank, uint32_t start, uint32_t end, const uint8_t *buffer)
-+{
-+ int res;
-+ uint32_t offset;
-+ struct flash_sector *sector;
-+ struct nrf52_info *chip = bank->driver_priv;
-+ assert(chip != NULL);
-+
-+ assert(start % chip->code_page_size == 0);
-+ assert(end % chip->code_page_size == 0);
-+
-+ /* Erase all sectors */
-+ for (offset = start; offset < end; offset += chip->code_page_size) {
-+ sector = nrf52_find_sector_by_address(bank, offset);
-+
-+ if (sector == NULL) {
-+ LOG_ERROR("Invalid sector @ 0x%08"PRIx32, offset);
-+ return ERROR_FLASH_SECTOR_INVALID;
-+ }
-+
-+ if (sector->is_protected == 1) {
-+ LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32, offset);
-+ return ERROR_FAIL;
-+ }
-+
-+ if (sector->is_erased != 1) { /* 1 = erased, 0= not erased, -1 = unknown */
-+ res = nrf52_erase_page(bank, chip, sector);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
-+ return res;
-+ }
-+ }
-+ sector->is_erased = 1;
-+ }
-+
-+ res = nrf52_nvmc_write_enable(chip);
-+ if (res != ERROR_OK)
-+ return res;
-+
-+ res = nrf52_ll_flash_write(chip, start, buffer, (end - start));
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Failed to write FLASH");
-+ nrf52_nvmc_read_only(chip);
-+ return res;
-+ }
-+
-+ return nrf52_nvmc_read_only(chip);
-+}
-+
-+static int nrf52_erase(struct flash_bank *bank, int first, int last)
-+{
-+ int res = ERROR_OK;
-+ struct nrf52_info *chip = bank->driver_priv;
-+ assert(chip != NULL);
-+
-+ /* For each sector to be erased */
-+ for (int s = first; s <= last && res == ERROR_OK; s++)
-+ res = nrf52_erase_page(bank, chip, &bank->sectors[s]);
-+
-+ return res;
-+}
-+
-+static int nrf52_code_flash_write(struct flash_bank *bank,
-+ struct nrf52_info *chip,
-+ const uint8_t *buffer, uint32_t offset, uint32_t count)
-+{
-+ int res;
-+ /* Need to perform reads to fill any gaps we need to preserve in the first page,
-+ before the start of buffer, or in the last page, after the end of buffer */
-+ uint32_t first_page = offset / chip->code_page_size;
-+ uint32_t last_page = DIV_ROUND_UP(offset+count, chip->code_page_size);
-+
-+ uint32_t first_page_offset = first_page * chip->code_page_size;
-+ uint32_t last_page_offset = last_page * chip->code_page_size;
-+
-+ LOG_DEBUG("Padding write from 0x%08"PRIx32"-0x%08"PRIx32" as 0x%08"PRIx32"-0x%08"PRIx32,
-+ offset, offset+count, first_page_offset, last_page_offset);
-+
-+ uint32_t page_cnt = last_page - first_page;
-+ uint8_t buffer_to_flash[page_cnt * chip->code_page_size];
-+
-+ /* Fill in any space between start of first page and start of buffer */
-+ uint32_t pre = offset - first_page_offset;
-+ if (pre > 0) {
-+ res = target_read_memory(bank->target, first_page_offset, 1, pre, buffer_to_flash);
-+ if (res != ERROR_OK)
-+ return res;
-+ }
-+
-+ /* Fill in main contents of buffer */
-+ memcpy(buffer_to_flash + pre, buffer, count);
-+
-+ /* Fill in any space between end of buffer and end of last page */
-+ uint32_t post = last_page_offset - (offset + count);
-+ if (post > 0) {
-+ /* Retrieve the full row contents from Flash */
-+ res = target_read_memory(bank->target, offset + count, 1, post, buffer_to_flash + pre + count);
-+ if (res != ERROR_OK)
-+ return res;
-+ }
-+
-+ return nrf52_write_pages(bank, first_page_offset, last_page_offset, buffer_to_flash);
-+}
-+
-+static int nrf52_uicr_flash_write(struct flash_bank *bank,
-+ struct nrf52_info *chip,
-+ const uint8_t *buffer, uint32_t offset, uint32_t count)
-+{
-+ int res;
-+ uint32_t nrf52_uicr_size = chip->code_page_size;
-+ uint8_t uicr[nrf52_uicr_size];
-+ struct flash_sector *sector = &bank->sectors[0];
-+
-+ if ((offset + count) > nrf52_uicr_size)
-+ return ERROR_FAIL;
-+
-+ res = target_read_memory(bank->target, NRF52_UICR_BASE_ADDR, 1, nrf52_uicr_size, uicr);
-+
-+ if (res != ERROR_OK)
-+ return res;
-+
-+ if (sector->is_erased != 1) {
-+ res = nrf52_erase_page(bank, chip, sector);
-+ if (res != ERROR_OK)
-+ return res;
-+ }
-+
-+ memcpy(&uicr[offset], buffer, count);
-+
-+ res = nrf52_nvmc_write_enable(chip);
-+ if (res != ERROR_OK)
-+ return res;
-+
-+ res = nrf52_ll_flash_write(chip, NRF52_UICR_BASE_ADDR, uicr, nrf52_uicr_size);
-+ if (res != ERROR_OK) {
-+ nrf52_nvmc_read_only(chip);
-+ return res;
-+ }
-+
-+ return nrf52_nvmc_read_only(chip);
-+}
-+
-+
-+static int nrf52_write(struct flash_bank *bank, const uint8_t *buffer,
-+ uint32_t offset, uint32_t count)
-+{
-+ struct nrf52_info *chip = bank->driver_priv;
-+ assert(chip != NULL);
-+
-+ return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
-+}
-+
-+
-+FLASH_BANK_COMMAND_HANDLER(nrf52_flash_bank_command)
-+{
-+ static struct nrf52_info *chip;
-+
-+ assert(bank != NULL);
-+
-+ switch (bank->base) {
-+ case NRF52_FLASH_BASE_ADDR:
-+ bank->bank_number = 0;
-+ break;
-+ case NRF52_UICR_BASE_ADDR:
-+ bank->bank_number = 1;
-+ break;
-+ default:
-+ LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
-+ return ERROR_FAIL;
-+ }
-+
-+ if (!chip) {
-+ /* Create a new chip */
-+ chip = calloc(1, sizeof(*chip));
-+ assert(chip != NULL);
-+
-+ chip->target = bank->target;
-+ }
-+
-+ switch (bank->base) {
-+ case NRF52_FLASH_BASE_ADDR:
-+ chip->bank[bank->bank_number].write = nrf52_code_flash_write;
-+ break;
-+ case NRF52_UICR_BASE_ADDR:
-+ chip->bank[bank->bank_number].write = nrf52_uicr_flash_write;
-+ break;
-+ }
-+
-+ chip->bank[bank->bank_number].probed = false;
-+ bank->driver_priv = chip;
-+
-+ return ERROR_OK;
-+}
-+
-+COMMAND_HANDLER(nrf52_handle_mass_erase_command)
-+{
-+ int res;
-+ struct flash_bank *bank = NULL;
-+ struct target *target = get_current_target(CMD_CTX);
-+
-+ res = get_flash_bank_by_addr(target, NRF52_FLASH_BASE_ADDR, true, &bank);
-+ if (res != ERROR_OK)
-+ return res;
-+
-+ assert(bank != NULL);
-+
-+ struct nrf52_info *chip = bank->driver_priv;
-+ assert(chip != NULL);
-+
-+ res = nrf52_erase_all(chip);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Failed to erase the chip");
-+ nrf52_protect_check(bank);
-+ return res;
-+ }
-+
-+ for (int i = 0; i < bank->num_sectors; i++)
-+ bank->sectors[i].is_erased = 1;
-+
-+ res = nrf52_protect_check(bank);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Failed to check chip's write protection");
-+ return res;
-+ }
-+
-+ res = get_flash_bank_by_addr(target, NRF52_UICR_BASE_ADDR, true, &bank);
-+ if (res != ERROR_OK)
-+ return res;
-+
-+ bank->sectors[0].is_erased = 1;
-+
-+ return ERROR_OK;
-+}
-+
-+static int nrf52_info(struct flash_bank *bank, char *buf, int buf_size)
-+{
-+ int res;
-+ uint32_t ficr[2];
-+ struct nrf52_info *chip = bank->driver_priv;
-+ assert(chip != NULL);
-+
-+ res = target_read_u32(chip->target, NRF52_FICR_CODEPAGESIZE_ADDR, &ficr[0]);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Couldn't read NVMC_READY register");
-+ return res;
-+ }
-+
-+ res = target_read_u32(chip->target, NRF52_FICR_CODESIZE_ADDR, &ficr[1]);
-+ if (res != ERROR_OK) {
-+ LOG_ERROR("Couldn't read NVMC_READY register");
-+ return res;
-+ }
-+
-+ snprintf(buf, buf_size,
-+ "\n--------nRF52 Series Device--------\n\n"
-+ "\n[factory information control block]\n"
-+ "code page size: %"PRIu32"B\n"
-+ "code memory size: %"PRIu32"kB\n",
-+ ficr[0],
-+ (ficr[1] * ficr[0]) / 1024);
-+
-+ return ERROR_OK;
-+}
-+
-+static const struct command_registration nrf52_exec_command_handlers[] = {
-+ {
-+ .name = "mass_erase",
-+ .handler = nrf52_handle_mass_erase_command,
-+ .mode = COMMAND_EXEC,
-+ .help = "Erase all flash contents of the chip.",
-+ },
-+ COMMAND_REGISTRATION_DONE
-+};
-+
-+static const struct command_registration nrf52_command_handlers[] = {
-+ {
-+ .name = "nrf52",
-+ .mode = COMMAND_ANY,
-+ .help = "nrf52 flash command group",
-+ .usage = "",
-+ .chain = nrf52_exec_command_handlers,
-+ },
-+ COMMAND_REGISTRATION_DONE
-+};
-+
-+struct flash_driver nrf52_flash = {
-+ .name = "nrf52",
-+ .commands = nrf52_command_handlers,
-+ .flash_bank_command = nrf52_flash_bank_command,
-+ .info = nrf52_info,
-+ .erase = nrf52_erase,
-+ .protect = nrf52_protect,
-+ .write = nrf52_write,
-+ .read = default_flash_read,
-+ .probe = nrf52_probe,
-+ .auto_probe = nrf52_auto_probe,
-+ .erase_check = default_flash_blank_check,
-+ .protect_check = nrf52_protect_check,
-+};
-diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
-index c1cbf1a..41a22ff 100644
---- a/tcl/target/nrf52.cfg
-+++ b/tcl/target/nrf52.cfg
-@@ -10,6 +10,13 @@ if { [info exists CHIPNAME] } {
- set _CHIPNAME nrf52
- }
-
-+# Work-area is a space in RAM used for flash programming, by default use 16kB.
-+if { [info exists WORKAREASIZE] } {
-+ set _WORKAREASIZE $WORKAREASIZE
-+} else {
-+ set _WORKAREASIZE 0x4000
-+}
-+
- if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
- } else {
-@@ -22,7 +29,15 @@ set _TARGETNAME $_CHIPNAME.cpu
- target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
- adapter_khz 10000
-+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
- if { ![using_hla] } {
- cortex_m reset_config sysresetreq
- }
-+
-+flash bank $_CHIPNAME.flash nrf52 0x00000000 0 1 1 $_TARGETNAME
-+flash bank $_CHIPNAME.uicr nrf52 0x10001000 0 1 1 $_TARGETNAME
-+
-+adapter_khz 1000
-+
-+$_TARGETNAME configure -event reset-end {}
--
2.28.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* bug#43852: [PATCH v2] gnu: Add riscv-openocd.
2020-10-10 14:02 ` [bug#43852] [PATCH v2] " Malte Frank Gerdes
@ 2020-10-22 14:49 ` Ludovic Courtès
0 siblings, 0 replies; 4+ messages in thread
From: Ludovic Courtès @ 2020-10-22 14:49 UTC (permalink / raw)
To: Malte Frank Gerdes
Cc: Ricardo Wurmus, Danny Milosavljevic, Andreas Enge, 43852-done,
Mathieu Othacehe
Hello,
Malte Frank Gerdes <malte.f.gerdes@gmail.com> skribis:
>>From 5be71d32e9694fadea411a267e36333697510bb1 Mon Sep 17 00:00:00 2001
> From: Malte Frank Gerdes <malte.f.gerdes@gmail.com>
> Date: Sat, 10 Oct 2020 15:24:46 +0200
> Subject: [PATCH 1/2] gnu: libjaylink: Update to 0.2.0
>
> * gnu/packages/embedded.scm (libjaylink): Update to 0.2.0
> [origin]: Substitute upstream repository location.
[...]
>>From de5299f976f54ef431e856ca15b045408495491b Mon Sep 17 00:00:00 2001
> From: Malte Frank Gerdes <malte.f.gerdes@gmail.com>
> Date: Sat, 10 Oct 2020 15:31:14 +0200
> Subject: [PATCH 2/2] gnu: openocd: Update to
> 9a877a83a1c8b1f105cdc0de46c5cbc4d9e8799e.
>
> * gnu/packages/embedded.scm (openocd): Update to 9a877a83a1c8b1f105cdc0de46c5cbc4d9e8799e.
> [version]: Substitute release with current master.
> [source]: Remove openocd-nrf52.patch
> [arguments]: Replace bootstrap build phase.
>
> * gnu/local.mk: Remove openocd-nrf52.patch.
> * gnu/packages/patches/openocd-nrf52.patch: Remove file.
I believe this addresses the concerns Andreas raised, so I’ve applied
them now.
(I’ve Cc’d Ricardo, Danny, and Mathieu, who also work in this area, just
so they notice.)
Thanks!
Ludo’.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-10-22 14:54 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-10-07 20:02 [bug#43852] [PATCH] gnu: Add riscv-openocd Malte Frank Gerdes
2020-10-09 19:02 ` Andreas Enge
2020-10-10 14:02 ` [bug#43852] [PATCH v2] " Malte Frank Gerdes
2020-10-22 14:49 ` bug#43852: " Ludovic Courtès
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