[bug#74242] [PATCH] gnu: Add python-vunit.

[bug#74242] [PATCH] gnu: Add python-vunit.

[Cayetano Santos via Guix-patches via]

* gnu/packages/fpga.scm (python-vunit): New variable.

Change-Id: Ieb16ec16928e6b0b2af6992fd9566cb946990dad
---
 gnu/packages/fpga.scm | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index c812ed3b7e..a6efa40fcd 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -433,6 +433,32 @@ (define-public python-myhdl
 a hardware description and verification language.")
     (license license:lgpl2.1+)))
 
+(define-public python-vunit
+  (package
+    (name "python-vunit")
+    (version "4.7.0")
+    (source
+     (origin
+       (method git-fetch)
+       (uri (git-reference
+             (url "https://github.com/VUnit/vunit")
+             (commit (string-append "v" version))
+             (recursive? #t)))
+       (file-name (git-file-name name version))
+       (sha256
+        (base32 "0s7j5bykbv34wgnxy5cl4zp6g0caidvzs8pd9yxjq341543xkjwm"))))
+    (build-system python-build-system)
+    ;; tests
+    (native-inputs (list python-pytest))
+    (inputs (list nvc python-pycodestyle python-pylint))
+    ;; tests
+    (propagated-inputs (list python python-colorama))
+    (home-page "https://vunit.github.io")
+    (synopsis "Open source unit testing framework for VHDL/SystemVerilog")
+    (description
+     "VUnit features the functionality needed to realize continuous and automated testing of HDL code.")
+    (license (list license:mpl2.0 license:asl2.0))))
+
 (define-public nvc
   (package
     (name "nvc")

base-commit: 673b924ac1e30a5d498e28859af365cf2bb4a508
-- 
2.46.0

[bug#74242] [PATCH v1] gnu: Add python-vunit.

[Cayetano Santos via Guix-patches via]

* gnu/packages/fpga.scm (python-vunit): New variable.

Change-Id: Ieb16ec16928e6b0b2af6992fd9566cb946990dad
---
 gnu/packages/fpga.scm | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index c812ed3b7e..2a0584cc1c 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -433,6 +433,30 @@ (define-public python-myhdl
 a hardware description and verification language.")
     (license license:lgpl2.1+)))
 
+(define-public python-vunit
+  (package
+    (name "python-vunit")
+    (version "4.7.0")
+    (source
+     (origin
+       (method git-fetch)
+       (uri (git-reference
+             (url "https://github.com/VUnit/vunit")
+             (commit (string-append "v" version))
+             (recursive? #t)))
+       (file-name (git-file-name name version))
+       (sha256
+        (base32 "0s7j5bykbv34wgnxy5cl4zp6g0caidvzs8pd9yxjq341543xkjwm"))))
+    (build-system python-build-system)
+    (arguments
+     '(#:tests? #f)) ;requires setuptools_scm >= 2.0.0, <3
+    (propagated-inputs (list python python-colorama))
+    (home-page "https://vunit.github.io")
+    (synopsis "Open source unit testing framework for VHDL/SystemVerilog")
+    (description
+     "VUnit features the functionality needed to realize continuous and automated testing of HDL code.")
+    (license (list license:mpl2.0 license:asl2.0))))
+
 (define-public nvc
   (package
     (name "nvc")

base-commit: 2a6d96425eea57dc6dd48a2bec16743046e32e06
-- 
2.46.0

bug#74242: [PATCH v1] gnu: Add python-vunit.

[Ludovic Courtès]

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Hello,

Cayetano Santos <csantosb@inventati.org> skribis:

> * gnu/packages/fpga.scm (python-vunit): New variable.
>
> Change-Id: Ieb16ec16928e6b0b2af6992fd9566cb946990dad

Finally applied, with the changes below.

Thanks!

Ludo’.


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diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 5c3faf2c94..9116a4f151 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -537,12 +537,16 @@ (define-public python-vunit
         (base32 "0s7j5bykbv34wgnxy5cl4zp6g0caidvzs8pd9yxjq341543xkjwm"))))
     (build-system python-build-system)
     (arguments
-     '(#:tests? #f)) ;requires setuptools_scm >= 2.0.0, <3
+     '(#:tests? #f))                ;XXX: requires setuptools_scm >= 2.0.0, <3
     (propagated-inputs (list python python-colorama))
     (home-page "https://vunit.github.io")
-    (synopsis "Open source unit testing framework for VHDL/SystemVerilog")
+    (synopsis "Unit testing framework for VHDL/SystemVerilog")
     (description
-     "VUnit features the functionality needed to realize continuous and automated testing of HDL code.")
+     "VUnit features the functionality needed to realize continuous and
+automated testing of HDL code.")
+
+    ;; According to 'LICENSE.rst', VUnit itself is under MPL but two
+    ;; subdirectories are under ASL.
     (license (list license:mpl2.0 license:asl2.0))))
 
 (define-public nvc