[bug#73837] [PATCH] gnu: iverilog: Update to 12.0.

[bug#73837] [PATCH] gnu: iverilog: Update to 12.0.

[Cayetano Santos via Guix-patches via]

* gnu/packages/fpga.scm (iverilog): Update to 12.0.

Change-Id: I55c3142aa41b190fef79572576cac6fc02473645
---

Iverilog 12 has a new home page. Update definition as for instructions in there.

 gnu/packages/fpga.scm | 45 +++++++++++++++++++++++++++++--------------
 1 file changed, 31 insertions(+), 14 deletions(-)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index b4ada59b9c..086dcce82a 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -40,6 +40,7 @@ (define-module (gnu packages fpga)
   #:use-module (gnu packages base)
   #:use-module (gnu packages bison)
   #:use-module (gnu packages boost)
+  #:use-module (gnu packages shells)
   #:use-module (gnu packages check)
   #:use-module (gnu packages cmake)
   #:use-module (gnu packages compression)
@@ -106,23 +107,39 @@ (define-public abc
 (define-public iverilog
   (package
     (name "iverilog")
-    (version "11.0")
-    (source (origin
-              (method url-fetch)
-              (uri
-               (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v11/"
-                              "verilog-" version ".tar.gz"))
-              (sha256
-               (base32
-                "1mamlrkpb2gb00g7xdddaknrvwi4jr4ng6cfjhwngzk3ddhqaiym"))))
+    (version "12.0")
+    (source
+     (origin
+       (method git-fetch)
+       (uri (git-reference
+             (url "https://github.com/steveicarus/iverilog")
+             (commit "v12_0")))
+       (file-name (git-file-name name version))
+       (sha256
+        (base32 "1cm3ksxyyp8ihs0as5c2nk3a0y2db8dmrrw0f9an3sl255smxn17"))))
     (build-system gnu-build-system)
     (arguments
-     `(#:make-flags (list (string-append "CC=" ,(cc-for-target)))))
-    (native-inputs
-     (list flex bison ghostscript zlib))   ; ps2pdf
-    (home-page "http://iverilog.icarus.com/")
+     (list
+      #:test-target "check"
+      #:make-flags #~(list (string-append "PREFIX="
+                                          #$output))
+      #:phases #~(modify-phases %standard-phases
+                   (delete 'bootstrap)
+                   (add-before 'configure 'autoconf
+                     (lambda _
+                       (invoke "chmod" "+x" "autoconf.sh")
+                       (invoke "./autoconf.sh"))))))
+    (native-inputs (list autoconf bison flex))
+    (inputs (list gawk
+                  gperf
+                  grep
+                  perl
+                  sed
+                  tcsh))
+    (home-page "https://steveicarus.github.io/iverilog")
     (synopsis "FPGA Verilog simulation and synthesis tool")
-    (description "Icarus Verilog is a Verilog simulation and synthesis tool.
+    (description
+     "Icarus Verilog is a Verilog simulation and synthesis tool.
 It operates as a compiler, compiling source code written in Verilog
 (IEEE-1364) into some target format.
 For batch simulation, the compiler can generate an intermediate form

base-commit: f443f5b0cd77cbbfa70cd915b4082ce32340127e
--
2.46.0

[bug#73837] [PATCH] gnu: iverilog: Update to 12.0.

[Z572]

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Cayetano Santos via Guix-patches via <guix-patches@gnu.org> writes:

It is best to use git send-email, see

https://guix.gnu.org/manual/devel/en/html_node/Sending-a-Patch-Series.html

> * gnu/packages/fpga.scm (iverilog): Update to 12.0.
>
> Change-Id: I55c3142aa41b190fef79572576cac6fc02473645
> ---
>
> Iverilog 12 has a new home page. Update definition as for instructions in there.

Please try to record these

* gnu/packages/fpga.scm (iverilog): Update to 12.0.
[source]: Switch to git-fetch.
[arguments]: Use G-expressions.
Set #:bootstrap-scripts to #~(list "autoconf.sh").
Set #:test-target to "check".
[home-page]: Update to new home page.
[native-inputs]: Add autoconf, gperf, remove ghostscript and zlib.

>
>  gnu/packages/fpga.scm | 45 +++++++++++++++++++++++++++++--------------
>  1 file changed, 31 insertions(+), 14 deletions(-)
>
> diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
> index b4ada59b9c..086dcce82a 100644
> --- a/gnu/packages/fpga.scm
> +++ b/gnu/packages/fpga.scm
> @@ -40,6 +40,7 @@ (define-module (gnu packages fpga)
>    #:use-module (gnu packages base)
>    #:use-module (gnu packages bison)
>    #:use-module (gnu packages boost)
> +  #:use-module (gnu packages shells)
>    #:use-module (gnu packages check)
>    #:use-module (gnu packages cmake)
>    #:use-module (gnu packages compression)
> @@ -106,23 +107,39 @@ (define-public abc
>  (define-public iverilog
>    (package
>      (name "iverilog")
> -    (version "11.0")
> -    (source (origin
> -              (method url-fetch)
> -              (uri
> -               (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v11/"
> -                              "verilog-" version ".tar.gz"))
> -              (sha256
> -               (base32
> -                "1mamlrkpb2gb00g7xdddaknrvwi4jr4ng6cfjhwngzk3ddhqaiym"))))
> +    (version "12.0")
> +    (source
> +     (origin
> +       (method git-fetch)
> +       (uri (git-reference
> +             (url "https://github.com/steveicarus/iverilog")
> +             (commit "v12_0")))

(commit
  (string-append "v" (string-replace-substring version "." "_")))

> +       (file-name (git-file-name name version))
> +       (sha256
> +        (base32 "1cm3ksxyyp8ihs0as5c2nk3a0y2db8dmrrw0f9an3sl255smxn17"))))
>      (build-system gnu-build-system)
>      (arguments
> -     `(#:make-flags (list (string-append "CC=" ,(cc-for-target)))))
> -    (native-inputs
> -     (list flex bison ghostscript zlib))   ; ps2pdf
> -    (home-page "http://iverilog.icarus.com/")
> +     (list
> +      #:test-target "check"
> +      #:make-flags #~(list (string-append "PREFIX="
> +                                          #$output))
> +      #:phases #~(modify-phases %standard-phases
> +                   (delete 'bootstrap)
> +                   (add-before 'configure 'autoconf
> +                     (lambda _
> +                       (invoke "chmod" "+x" "autoconf.sh")
> +                       (invoke "./autoconf.sh"))))))

just use #:bootstrap-scripts #~(list "autoconf.sh") , no need change
#:phases.

> +    (native-inputs (list autoconf bison flex))

gperf should go to native-inputs. if you try cross-compiling this
package, will find that.

> +    (inputs (list gawk
> +                  gperf
> +                  grep
> +                  perl
> +                  sed
> +                  tcsh))

other inputs is no needed. by defaults gawk, grep, sed is included (see
guix/build-system/gnu.scm (standard-packages) and
gnu/packages/commencement.scm (%final-inputs) ).

And without them, build also success.

> +    (home-page "https://steveicarus.github.io/iverilog")
>      (synopsis "FPGA Verilog simulation and synthesis tool")
> -    (description "Icarus Verilog is a Verilog simulation and synthesis tool.
> +    (description
> +     "Icarus Verilog is a Verilog simulation and synthesis tool.
>  It operates as a compiler, compiling source code written in Verilog
>  (IEEE-1364) into some target format.
>  For batch simulation, the compiler can generate an intermediate form
>
> base-commit: f443f5b0cd77cbbfa70cd915b4082ce32340127e

here is patch after the modification.


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From 6b57079fac6dc4c5b1cf015cc5a38c0e9ae1c60f Mon Sep 17 00:00:00 2001
Message-ID: <6b57079fac6dc4c5b1cf015cc5a38c0e9ae1c60f.1729080767.git.zhengjunjie@iscas.ac.cn>
From: Cayetano Santos <csantosb@inventati.org>
Date: Wed, 16 Oct 2024 12:19:11 +0200
Subject: [PATCH] gnu: iverilog: Update to 12.0.

* gnu/packages/fpga.scm (iverilog): Update to 12.0.
[source]: Switch to git-fetch.
[arguments]: Use G-expressions.
Set #:bootstrap-scripts to #~(list "autoconf.sh").
Set #:test-target to "check".
[home-page]: Update to new home page.
[native-inputs]: Add autoconf, gperf, remove ghostscript and zlib.

Change-Id: I55c3142aa41b190fef79572576cac6fc02473645
---
 gnu/packages/fpga.scm | 34 ++++++++++++++++++++--------------
 1 file changed, 20 insertions(+), 14 deletions(-)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 4c713aab0b8..77f481751bd 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -107,23 +107,29 @@ (define-public abc
 (define-public iverilog
   (package
     (name "iverilog")
-    (version "11.0")
-    (source (origin
-              (method url-fetch)
-              (uri
-               (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v11/"
-                              "verilog-" version ".tar.gz"))
-              (sha256
-               (base32
-                "1mamlrkpb2gb00g7xdddaknrvwi4jr4ng6cfjhwngzk3ddhqaiym"))))
+    (version "12.0")
+    (source
+     (origin
+       (method git-fetch)
+       (uri (git-reference
+             (url "https://github.com/steveicarus/iverilog")
+             (commit
+              (string-append "v" (string-replace-substring version "." "_")))))
+       (file-name (git-file-name name version))
+       (sha256
+        (base32 "1cm3ksxyyp8ihs0as5c2nk3a0y2db8dmrrw0f9an3sl255smxn17"))))
     (build-system gnu-build-system)
     (arguments
-     `(#:make-flags (list (string-append "CC=" ,(cc-for-target)))))
-    (native-inputs
-     (list flex bison ghostscript zlib))   ; ps2pdf
-    (home-page "http://iverilog.icarus.com/")
+     (list
+      #:test-target "check"
+      #:make-flags #~(list (string-append "PREFIX="
+                                          #$output))
+      #:bootstrap-scripts #~(list "autoconf.sh")))
+    (native-inputs (list autoconf bison flex gperf))
+    (home-page "https://steveicarus.github.io/iverilog")
     (synopsis "FPGA Verilog simulation and synthesis tool")
-    (description "Icarus Verilog is a Verilog simulation and synthesis tool.
+    (description
+     "Icarus Verilog is a Verilog simulation and synthesis tool.
 It operates as a compiler, compiling source code written in Verilog
 (IEEE-1364) into some target format.
 For batch simulation, the compiler can generate an intermediate form

base-commit: b3b98151f30552357b91154deb6cc71696af5537
-- 
2.46.0


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[bug#73837] [PATCH] gnu: iverilog: Update to 12.0.

[Cayetano Santos via Guix-patches via]

>mer. 16 oct. 2024 at 20:20, Z572 <zhengjunjie@iscas.ac.cn> wrote:

> Cayetano Santos via Guix-patches via <guix-patches@gnu.org> writes:

> It is best to use git send-email, see

I’m using send-email (?)

> And without them, build also success.

There is just a couple of warnings:

  warning: no binary for interpreter `perl' found in $PATH
  warning: no binary for interpreter `csh' found in $PATH

I included perl and tcsh to avoid these.

> here is patch after the modification.

Other than the warnings, fine with me. Any action from my side ?

[bug#73837] [PATCH] gnu: iverilog: Update to 12.0.

[Z572]

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Cayetano Santos <csantosb@inventati.org> writes:

>>mer. 16 oct. 2024 at 20:20, Z572 <zhengjunjie@iscas.ac.cn> wrote:
>
>> Cayetano Santos via Guix-patches via <guix-patches@gnu.org> writes:
>
>> It is best to use git send-email, see
>
> I’m using send-email (?)

Not sure why some people send emails containing patch that are not sent from their own mailbox

e.g.
Cayetano Santos via Guix-patches via <guix-patches@gnu.org>



>
>> And without them, build also success.
>
> There is just a couple of warnings:
>
>   warning: no binary for interpreter `perl' found in $PATH
>   warning: no binary for interpreter `csh' found in $PATH
>
> I included perl and tcsh to avoid these.

In general, they may be needed for development scripts, so packaging
does not require them. If packaging fails, you can pay attention to see
if there is a lack of dependencies here

>
>> here is patch after the modification.
>
> Other than the warnings, fine with me. Any action from my side ?

If there is no problem, I will push it to the warehouse later

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