From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mp2 ([2001:41d0:2:4a6f::]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) by ms11 with LMTPS id yNK7DazAgV/JcAAA0tVLHw (envelope-from ) for ; Sat, 10 Oct 2020 14:09:48 +0000 Received: from aspmx1.migadu.com ([2001:41d0:2:4a6f::]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) by mp2 with LMTPS id YLeOCazAgV+2fgAAB5/wlQ (envelope-from ) for ; Sat, 10 Oct 2020 14:09:48 +0000 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by aspmx1.migadu.com (Postfix) with ESMTPS id 7A0749401DF for ; Sat, 10 Oct 2020 14:09:47 +0000 (UTC) Received: from localhost ([::1]:59664 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kRFZB-0001bT-Fm for larch@yhetil.org; Sat, 10 Oct 2020 10:09:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kRFTe-0001z2-Hl for guix-patches@gnu.org; Sat, 10 Oct 2020 10:04:03 -0400 Received: from debbugs.gnu.org ([209.51.188.43]:54821) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kRFTe-0004uI-8K for guix-patches@gnu.org; Sat, 10 Oct 2020 10:04:02 -0400 Received: from Debian-debbugs by debbugs.gnu.org with local (Exim 4.84_2) (envelope-from ) id 1kRFTe-0007Cz-4P for guix-patches@gnu.org; Sat, 10 Oct 2020 10:04:02 -0400 X-Loop: help-debbugs@gnu.org Subject: [bug#43852] [PATCH v2] gnu: Add riscv-openocd. Resent-From: Malte Frank Gerdes Original-Sender: "Debbugs-submit" Resent-CC: guix-patches@gnu.org Resent-Date: Sat, 10 Oct 2020 14:04:02 +0000 Resent-Message-ID: Resent-Sender: help-debbugs@gnu.org X-GNU-PR-Message: followup 43852 X-GNU-PR-Package: guix-patches X-GNU-PR-Keywords: patch To: Andreas Enge Cc: 43852@debbugs.gnu.org Received: via spool by 43852-submit@debbugs.gnu.org id=B43852.160233859327654 (code B ref 43852); Sat, 10 Oct 2020 14:04:02 +0000 Received: (at 43852) by debbugs.gnu.org; 10 Oct 2020 14:03:13 +0000 Received: from localhost ([127.0.0.1]:38134 helo=debbugs.gnu.org) by debbugs.gnu.org with esmtp (Exim 4.84_2) (envelope-from ) id 1kRFSh-0007Bo-6J for submit@debbugs.gnu.org; Sat, 10 Oct 2020 10:03:13 -0400 Received: from mail-ej1-f42.google.com ([209.85.218.42]:37144) by debbugs.gnu.org with esmtp (Exim 4.84_2) (envelope-from ) id 1kRFSc-0007BH-Mz for 43852@debbugs.gnu.org; Sat, 10 Oct 2020 10:03:02 -0400 Received: by mail-ej1-f42.google.com with SMTP id e22so17137763ejr.4 for <43852@debbugs.gnu.org>; Sat, 10 Oct 2020 07:02:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:references:date:in-reply-to:message-id :user-agent:mime-version; bh=BUjXOkOf4LF5riKDrUVUo9rwTcIXWjpJ5NcOv8/6Wjs=; b=T1qZoxMKBkHUjVRZQ49DLLVHqlbm3O0jerms/X03KsyPPYOya8FuCOw0kaT8XIIoCX o2VWzH0/cjyHaojRDRBBwTqCBKDCsJ+Kx5cA/003WRa/TpJ8+/UV45bLx7yGro4/WUNG kqOo1ch7DKWgxBLV5Pkpgk4GmJ9PZTwdxtEMC30I2G+vksaVNFetMztaZHllPUNQiPVt tNjucBOQTd57o1N2wVKzec+aPtzzx8g+y5SZEYx+US7aY/Ss5t/ounyBA/2vPcvtlTRN IDeAzCd6+4tuhRfKkJUQtRtsDlT20UKoUYVyQf8btk7MNHZvyIcqAvEASN4CcgLKJWyh o1bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version; bh=BUjXOkOf4LF5riKDrUVUo9rwTcIXWjpJ5NcOv8/6Wjs=; b=NCpD0CQctCShG06RMu+F4NqeLdhsmM1V6AnlkDCPwZW86A36aMWPI1cFATYFhm1Cqu mD5J54+zQboekCtgf0bbMprqto6KiRWmeBBxKFl+RtBooj+lvZiz114GclABGTkZOkh3 EDIouEDRhSvLkJp3td+rIkKkg0EaXy2aX3XvTtzpyWY+CCN3bHmAk6tGmen2cxU2Ezui WL2h2QY61PIyCKd3qKByljS2fySb9S6FFA7V/PocQVKa21oPsI4nM+zQ6H7YoN7btI7H xhNnWjqEzN4NGcVpEh26DVTPleZLx1y3rhpFwm/y8Uy7xfFsCyTZ/o6QszpuuveXpkNK 6jjQ== X-Gm-Message-State: AOAM5310fpqlQgRoVDpurHhyr3lVGydyIBBfpTzP/HM6Nyl0Oebyi7rb /gFzQD3yscJHa7keNXzKg4oNUJb1f1Ej4w== X-Google-Smtp-Source: ABdhPJxDe3eOjGnCiRcIWok79xzhtsNFVB2F9FCjaDIFf+yvTzGhjVdkuo+8DdZQUn+WGgAGIrDXLQ== X-Received: by 2002:a17:906:b285:: with SMTP id q5mr19814113ejz.470.1602338572563; Sat, 10 Oct 2020 07:02:52 -0700 (PDT) Received: from Morphium (ip-84-118-73-55.unity-media.net. [84.118.73.55]) by smtp.gmail.com with ESMTPSA id p16sm8016173ejz.103.2020.10.10.07.02.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2020 07:02:51 -0700 (PDT) From: Malte Frank Gerdes References: <86lfgh6bzy.fsf@gmail.com> <20201009190257.GA2052@jurong> Date: Sat, 10 Oct 2020 16:02:50 +0200 In-Reply-To: <20201009190257.GA2052@jurong> (Andreas Enge's message of "Fri, 9 Oct 2020 21:02:57 +0200") Message-ID: <86blha2n79.fsf_-_@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux) MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-=-=" X-Spam-Score: 0.7 (/) X-BeenThere: debbugs-submit@debbugs.gnu.org X-Mailman-Version: 2.1.18 Precedence: list X-Spam-Score: -1.0 (-) X-BeenThere: guix-patches@gnu.org List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: guix-patches-bounces+larch=yhetil.org@gnu.org Sender: "Guix-patches" X-Scanner: scn0 Authentication-Results: aspmx1.migadu.com; dkim=fail (rsa verify failed) header.d=gmail.com header.s=20161025 header.b=T1qZoxMK; dmarc=fail reason="SPF not aligned (relaxed)" header.from=gmail.com (policy=none); spf=pass (aspmx1.migadu.com: domain of guix-patches-bounces@gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=guix-patches-bounces@gnu.org X-Spam-Score: 1.59 X-TUID: XIlHQ+dWrWlD --=-=-= Content-Type: text/plain Andreas Enge writes: > Hello, > > since I am speaking as someone who does not know what these packages are > about, please take what follows with a grain of salt. Feedback is always good! especially when it leads to realizing how it should actually be done. > On Wed, Oct 07, 2020 at 10:02:09PM +0200, Malte Frank Gerdes wrote: >> libjaylink ... is >> ... available as a package. The available package ... >> ... is too old ... >> ... should I do something? > > Written like this, I would say you could try updating it, independently > of your target package. Then the question is whether you break anything > else: > guix refresh -l libjaylink > A single dependent package: openocd@0.10.0 > > So there already is an openocd, which maybe should be updated at the same > time? The problem was: i didn't realize that libjaylink has a new release and that it's actually possible to clone it; because the official upstream repo seems to be locked behind a login. But there is a mirror of it on repo.or.cz - which i'm now using. > And do you really need a new package, or could it be enough to provide > more inputs or configuration flags to the existing one? Otherwise, how > about inheriting? The name also is weird, see the section in the manual; > we normally keep the upstream project name. I used riscv/riscv-openocd as the upstream repo (github), but it seems that this isn't necessary. So i'm now just updating the package we already have. It doesn't have a new release, so i had to use the git master. Malte --=-=-= Content-Type: text/x-patch Content-Disposition: inline; filename=0001-gnu-libjaylink-Update-to-0.2.0.patch >From 5be71d32e9694fadea411a267e36333697510bb1 Mon Sep 17 00:00:00 2001 From: Malte Frank Gerdes Date: Sat, 10 Oct 2020 15:24:46 +0200 Subject: [PATCH 1/2] gnu: libjaylink: Update to 0.2.0 * gnu/packages/embedded.scm (libjaylink): Update to 0.2.0 [origin]: Substitute upstream repository location. --- gnu/packages/embedded.scm | 52 ++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/gnu/packages/embedded.scm b/gnu/packages/embedded.scm index f9f0e04238..1eacb72a45 100644 --- a/gnu/packages/embedded.scm +++ b/gnu/packages/embedded.scm @@ -458,35 +458,31 @@ languages are C and C++.") ,@(package-arguments gdb))))) (define-public libjaylink - ;; No release tarballs available. - (let ((commit "699b7001d34a79c8e7064503dde1bede786fd7f0") - (revision "2")) - (package - (name "libjaylink") - (version (string-append "0.1.0-" revision "." - (string-take commit 7))) - (source (origin - (method git-fetch) - (uri (git-reference - (url "https://git.zapb.de/libjaylink.git") - (commit commit))) - (file-name (string-append name "-" version "-checkout")) - (sha256 - (base32 - "034872d44myycnzn67v5b8ixrgmg8sk32aqalvm5x7108w2byww1")))) - (build-system gnu-build-system) - (native-inputs - `(("autoconf" ,autoconf) - ("automake" ,automake) - ("libtool" ,libtool) - ("pkg-config" ,pkg-config))) - (inputs - `(("libusb" ,libusb))) - (home-page "https://repo.or.cz/w/libjaylink.git") - (synopsis "Library to interface Segger J-Link devices") - (description "libjaylink is a shared library written in C to access + (package + (name "libjaylink") + (version "0.2.0") + (source (origin + (method git-fetch) + (uri (git-reference + (url "https://repo.or.cz/libjaylink.git") + (commit version))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "0ndyfh51hiqyv2yscpj6qd091w7myxxjid3a6rx8f6k233vy826q")))) + (build-system gnu-build-system) + (native-inputs + `(("autoconf" ,autoconf) + ("automake" ,automake) + ("libtool" ,libtool) + ("pkg-config" ,pkg-config))) + (inputs + `(("libusb" ,libusb))) + (home-page "https://repo.or.cz/w/libjaylink.git") + (synopsis "Library to interface Segger J-Link devices") + (description "libjaylink is a shared library written in C to access SEGGER J-Link and compatible devices.") - (license license:gpl2+)))) + (license license:gpl2+))) (define-public jimtcl (package -- 2.28.0 --=-=-= Content-Type: text/x-patch; charset=utf-8 Content-Disposition: inline; filename=0002-gnu-openocd-Update-to-9a877a83a1c8b1f105cdc0de46c5cb.patch Content-Transfer-Encoding: quoted-printable >From de5299f976f54ef431e856ca15b045408495491b Mon Sep 17 00:00:00 2001 From: Malte Frank Gerdes Date: Sat, 10 Oct 2020 15:31:14 +0200 Subject: [PATCH 2/2] gnu: openocd: Update to 9a877a83a1c8b1f105cdc0de46c5cbc4d9e8799e. * gnu/packages/embedded.scm (openocd): Update to 9a877a83a1c8b1f105cdc0de46= c5cbc4d9e8799e. [version]: Substitute release with current master. [source]: Remove openocd-nrf52.patch [arguments]: Replace bootstrap build phase. * gnu/local.mk: Remove openocd-nrf52.patch. * gnu/packages/patches/openocd-nrf52.patch: Remove file. --- gnu/local.mk | 2 +- gnu/packages/embedded.scm | 124 ++-- gnu/packages/patches/openocd-nrf52.patch | 827 ----------------------- 3 files changed, 65 insertions(+), 888 deletions(-) delete mode 100644 gnu/packages/patches/openocd-nrf52.patch diff --git a/gnu/local.mk b/gnu/local.mk index f3b5b17e84..70a563cf99 100644 --- a/gnu/local.mk +++ b/gnu/local.mk @@ -37,6 +37,7 @@ # Copyright =C2=A9 2020 Brice Waegeneire # Copyright =C2=A9 2020 Tanguy Le Carrour # Copyright =C2=A9 2020 Martin Becze +# Copyright =C2=A9 2020 Malte Frank Gerdes # # This file is part of GNU Guix. # @@ -1385,7 +1386,6 @@ dist_patch_DATA =3D \ %D%/packages/patches/openfoam-4.1-cleanup.patch \ %D%/packages/patches/openjdk-10-idlj-reproducibility.patch \ %D%/packages/patches/openmpi-mtl-priorities.patch \ - %D%/packages/patches/openocd-nrf52.patch \ %D%/packages/patches/openssh-hurd.patch \ %D%/packages/patches/openresolv-restartcmd-guix.patch \ %D%/packages/patches/openscad-parser-boost-1.72.patch \ diff --git a/gnu/packages/embedded.scm b/gnu/packages/embedded.scm index 1eacb72a45..cc26b17ea6 100644 --- a/gnu/packages/embedded.scm +++ b/gnu/packages/embedded.scm @@ -514,67 +514,71 @@ language.") (license license:bsd-2))) =20 (define-public openocd - (package - (name "openocd") - (version "0.10.0") - (source (origin - (method url-fetch) - (uri (string-append "mirror://sourceforge/openocd/openocd/" - version "/openocd-" version ".tar.gz")) - (sha256 - (base32 - "09p57y3c2spqx4vjjlz1ljm1lcd0j9q8g76ywxqgn3yc34wv18zd")) - ;; FIXME: Remove after nrf52 patch is merged. - (patches - (search-patches "openocd-nrf52.patch")))) - (build-system gnu-build-system) - (native-inputs - `(("autoconf" ,autoconf) - ("automake" ,automake) - ("libtool" ,libtool) - ("pkg-config" ,pkg-config))) - (inputs - `(("hidapi" ,hidapi) - ("jimtcl" ,jimtcl) - ("libftdi" ,libftdi) - ("libjaylink" ,libjaylink) - ("libusb-compat" ,libusb-compat))) - (arguments - '(#:configure-flags - (append (list "--disable-werror" - "--enable-sysfsgpio" - "--disable-internal-jimtcl" - "--disable-internal-libjaylink") - (map (lambda (programmer) - (string-append "--enable-" programmer)) - '("amtjtagaccel" "armjtagew" "buspirate" "ftdi" - "gw16012" "jlink" "opendous" "osbdm" - "parport" "aice" "cmsis-dap" "dummy" "jtag_vpi" - "remote-bitbang" "rlink" "stlink" "ti-icdi" "ulink" - "usbprog" "vsllink" "usb-blaster-2" "usb_blaster" - "presto" "openjtag"))) - #:phases - (modify-phases %standard-phases - ;; Required because of patched sources. - (add-before 'configure 'autoreconf - (lambda _ (invoke "autoreconf" "-vfi") #t)) - (add-after 'autoreconf 'change-udev-group - (lambda _ - (substitute* "contrib/60-openocd.rules" - (("plugdev") "dialout")) - #t)) - (add-after 'install 'install-udev-rules - (lambda* (#:key outputs #:allow-other-keys) - (install-file "contrib/60-openocd.rules" - (string-append - (assoc-ref outputs "out") - "/lib/udev/rules.d/")) - #t))))) - (home-page "http://openocd.org") - (synopsis "On-Chip Debugger") - (description "OpenOCD provides on-chip programming and debugging suppo= rt + (let ((commit "9a877a83a1c8b1f105cdc0de46c5cbc4d9e8799e") + (revision "0")) + (package + (name "openocd") + (version (string-append "0.10.0-" revision "." + (string-take commit 7))) + (source (origin + (method git-fetch) + (uri (git-reference + (url "https://git.code.sf.net/p/openocd/code") + (commit commit))) + (file-name (string-append name "-" version "-checkout")) + (sha256 + (base32 + "1q536cp80v2bcy6xwk08f1r2ljyw13jchx3a1z7d3ni3vqql7rc6"))= )) + (build-system gnu-build-system) + (native-inputs + `(("autoconf" ,autoconf) + ("automake" ,automake) + ("libtool" ,libtool) + ("which" ,base:which) + ("pkg-config" ,pkg-config))) + (inputs + `(("hidapi" ,hidapi) + ("jimtcl" ,jimtcl) + ("libftdi" ,libftdi) + ("libjaylink" ,libjaylink) + ("libusb-compat" ,libusb-compat))) + (arguments + '(#:configure-flags + (append (list "--disable-werror" + "--enable-sysfsgpio" + "--disable-internal-jimtcl" + "--disable-internal-libjaylink") + (map (lambda (programmer) + (string-append "--enable-" programmer)) + '("amtjtagaccel" "armjtagew" "buspirate" "ftdi" + "gw16012" "jlink" "opendous" "osbdm" + "parport" "aice" "cmsis-dap" "dummy" "jtag_vpi" + "remote-bitbang" "rlink" "stlink" "ti-icdi" "ulink" + "usbprog" "vsllink" "usb-blaster-2" "usb_blaster" + "presto" "openjtag"))) + #:phases + (modify-phases %standard-phases + (replace 'bootstrap + (lambda _ + (patch-shebang "bootstrap") + (invoke "./bootstrap" "nosubmodule"))) + (add-after 'autoreconf 'change-udev-group + (lambda _ + (substitute* "contrib/60-openocd.rules" + (("plugdev") "dialout")) + #t)) + (add-after 'install 'install-udev-rules + (lambda* (#:key outputs #:allow-other-keys) + (install-file "contrib/60-openocd.rules" + (string-append + (assoc-ref outputs "out") + "/lib/udev/rules.d/")) + #t))))) + (home-page "http://openocd.org") + (synopsis "On-Chip Debugger") + (description "OpenOCD provides on-chip programming and debugging sup= port with a layered architecture of JTAG interface and TAP support.") - (license license:gpl2+))) + (license license:gpl2+)))) =20 ;; The commits for all propeller tools are the stable versions published at ;; https://github.com/propellerinc/propgcc in the release_1_0. According = to diff --git a/gnu/packages/patches/openocd-nrf52.patch b/gnu/packages/patche= s/openocd-nrf52.patch deleted file mode 100644 index 0ec4348cb4..0000000000 --- a/gnu/packages/patches/openocd-nrf52.patch +++ /dev/null @@ -1,827 +0,0 @@ -This patch adds support for nRF52 series devices. It is patchset 7 from -, which has been tested, but not -merged yet in master. - -From: Michael Dietz -Date: Mon, 30 May 2016 12:50:44 +0000 (-0700) -Subject: Added support for nRF52 Series Devices. -X-Git-Url: http://openocd.zylin.com/gitweb?p=3Dopenocd.git;a=3Dcommitdiff_= plain;h=3D9ba15633e221d9d72e320372ba8f49d3f30d4bce - -Added support for nRF52 Series Devices. - -Both nrf52.c and nrf52.cfg are based off of previous nRF51 files. -- Some possible race conditions with NVMC have been fixed in nRF52.c -- Removed nrf51_get_probed_chip_if_halted() as the core does not have to b= e halted to perform operations where it is called. -- Only registers that are needed by openOCD are defined, some registers in= nRF51 don't exist in nRF52 and are removed. -- Some all around cleanup has been done. -- The protection mechanism is completely different on nRF52 and this has n= ot been implemented yet - just prints a warning and returns for now. - -Change-Id: I4dd42c86f33f450709bb981806c2655f04aa6201 -Signed-off-by: Michael Dietz ---- - -diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am -index 727e4f2..839667c 100644 ---- a/src/flash/nor/Makefile.am -+++ b/src/flash/nor/Makefile.am -@@ -36,6 +36,7 @@ NOR_DRIVERS =3D \ - %D%/niietcm4.c \ - %D%/non_cfi.c \ - %D%/nrf51.c \ -+ %D%/nrf52.c \ - %D%/numicro.c \ - %D%/ocl.c \ - %D%/pic32mx.c \ -diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c -index 56a5cb2..071273e 100644 ---- a/src/flash/nor/drivers.c -+++ b/src/flash/nor/drivers.c -@@ -48,6 +48,7 @@ extern struct flash_driver mdr_flash; - extern struct flash_driver mrvlqspi_flash; - extern struct flash_driver niietcm4_flash; - extern struct flash_driver nrf51_flash; -+extern struct flash_driver nrf52_flash; - extern struct flash_driver numicro_flash; - extern struct flash_driver ocl_flash; - extern struct flash_driver pic32mx_flash; -@@ -100,6 +101,7 @@ static struct flash_driver *flash_drivers[] =3D { - &mrvlqspi_flash, - &niietcm4_flash, - &nrf51_flash, -+ &nrf52_flash, - &numicro_flash, - &ocl_flash, - &pic32mx_flash, -diff --git a/src/flash/nor/nrf52.c b/src/flash/nor/nrf52.c -new file mode 100644 -index 0000000..7f2bd35 ---- /dev/null -+++ b/src/flash/nor/nrf52.c -@@ -0,0 +1,733 @@ -+/************************************************************************= *** -+ * Copyright (C) 2013 Synapse Product Development = * -+ * Andrey Smirnov = * -+ * Angus Gratton = * -+ * Erdem U. Altunyurt = * -+ * = * -+ * This program is free software; you can redistribute it and/or modify= * -+ * it under the terms of the GNU General Public License as published by= * -+ * the Free Software Foundation; either version 2 of the License, or = * -+ * (at your option) any later version. = * -+ * = * -+ * This program is distributed in the hope that it will be useful, = * -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of = * -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the = * -+ * GNU General Public License for more details. = * -+ * = * -+ * You should have received a copy of the GNU General Public License = * -+ * along with this program. If not, see = . * -+ ************************************************************************= ***/ -+ -+#ifdef HAVE_CONFIG_H -+#include "config.h" -+#endif -+ -+#include -+ -+#include "imp.h" -+#include -+#include -+#include -+ -+/* nRF52 Register addresses used by openOCD. */ -+#define NRF52_FLASH_BASE_ADDR (0x0) -+ -+#define NRF52_FICR_BASE_ADDR (0x10000000) -+#define NRF52_FICR_CODEPAGESIZE_ADDR (NRF52_FICR_BASE_ADDR | 0x010) -+#define NRF52_FICR_CODESIZE_ADDR (NRF52_FICR_BASE_ADDR | 0x014) -+ -+#define NRF52_UICR_BASE_ADDR (0x10001000) -+ -+#define NRF52_NVMC_BASE_ADDR (0x4001E000) -+#define NRF52_NVMC_READY_ADDR (NRF52_NVMC_BASE_ADDR | 0x400) -+#define NRF52_NVMC_CONFIG_ADDR (NRF52_NVMC_BASE_ADDR | 0x504) -+#define NRF52_NVMC_ERASEPAGE_ADDR (NRF52_NVMC_BASE_ADDR | 0x508) -+#define NRF52_NVMC_ERASEALL_ADDR (NRF52_NVMC_BASE_ADDR | 0x50C) -+#define NRF52_NVMC_ERASEUICR_ADDR (NRF52_NVMC_BASE_ADDR | 0x514) -+ -+/* nRF52 bit fields. */ -+enum nrf52_nvmc_config_bits { -+ NRF52_NVMC_CONFIG_REN =3D 0x0, -+ NRF52_NVMC_CONFIG_WEN =3D 0x01, -+ NRF52_NVMC_CONFIG_EEN =3D 0x02 -+}; -+ -+enum nrf52_nvmc_ready_bits { -+ NRF52_NVMC_BUSY =3D 0x0, -+ NRF52_NVMC_READY =3D 0x01 -+}; -+ -+/* nRF52 state information. */ -+struct nrf52_info { -+ uint32_t code_page_size; /* Size of FLASH page in bytes. */ -+ uint32_t code_memory_size; /* Size of Code FLASH region in bytes. */ -+ -+ struct { -+ bool probed; -+ int (*write) (struct flash_bank *bank, -+ struct nrf52_info *chip, -+ const uint8_t *buffer, uint32_t offset, uint32_t count); -+ } bank[2]; /* There are two regions in nRF52 FLASH - Code and UICR. */ -+ struct target *target; -+}; -+ -+static int nrf52_protect_check(struct flash_bank *bank); -+ -+static int nrf52_probe(struct flash_bank *bank) -+{ -+ int res; -+ struct nrf52_info *chip =3D bank->driver_priv; -+ assert(chip !=3D NULL); -+ -+ res =3D target_read_u32(chip->target, -+ NRF52_FICR_CODEPAGESIZE_ADDR, -+ &chip->code_page_size); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Couldn't read code page size"); -+ return res; -+ } -+ -+ res =3D target_read_u32(chip->target, -+ NRF52_FICR_CODESIZE_ADDR, -+ &chip->code_memory_size); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Couldn't read code memory size"); -+ return res; -+ } -+ -+ chip->code_memory_size =3D chip->code_memory_size * chip->code_page_size; -+ -+ if (bank->base =3D=3D NRF52_FLASH_BASE_ADDR) { -+ bank->size =3D chip->code_memory_size; -+ bank->num_sectors =3D bank->size / chip->code_page_size; -+ bank->sectors =3D calloc(bank->num_sectors, -+ sizeof((bank->sectors)[0])); -+ if (!bank->sectors) -+ return ERROR_FLASH_BANK_NOT_PROBED; -+ -+ /* Fill out the sector information: All nRF51 sectors are the same size= . */ -+ for (int i =3D 0; i < bank->num_sectors; i++) { -+ bank->sectors[i].size =3D chip->code_page_size; -+ bank->sectors[i].offset =3D i * chip->code_page_size; -+ -+ /* Mark as unknown. */ -+ bank->sectors[i].is_erased =3D -1; -+ bank->sectors[i].is_protected =3D -1; -+ } -+ -+ nrf52_protect_check(bank); -+ -+ chip->bank[0].probed =3D true; -+ } else { /* This is the UICR bank. */ -+ bank->size =3D chip->code_page_size; -+ bank->num_sectors =3D 1; -+ bank->sectors =3D calloc(bank->num_sectors, -+ sizeof((bank->sectors)[0])); -+ if (!bank->sectors) -+ return ERROR_FLASH_BANK_NOT_PROBED; -+ -+ bank->sectors[0].size =3D bank->size; -+ bank->sectors[0].offset =3D 0; -+ -+ bank->sectors[0].is_erased =3D -1; -+ bank->sectors[0].is_protected =3D -1; -+ -+ chip->bank[1].probed =3D true; -+ } -+ -+ return ERROR_OK; -+} -+ -+static int nrf52_bank_is_probed(struct flash_bank *bank) -+{ -+ struct nrf52_info *chip =3D bank->driver_priv; -+ assert(chip !=3D NULL); -+ -+ return chip->bank[bank->bank_number].probed; -+} -+ -+static int nrf52_auto_probe(struct flash_bank *bank) -+{ -+ if (!nrf52_bank_is_probed(bank)) -+ return nrf52_probe(bank); -+ else -+ return ERROR_OK; -+} -+ -+static int nrf52_wait_for_nvmc(struct nrf52_info *chip) -+{ -+ int res; -+ uint32_t ready; -+ int timeout =3D 100; -+ -+ do { -+ res =3D target_read_u32(chip->target, NRF52_NVMC_READY_ADDR, &ready); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Couldn't read NVMC_READY register"); -+ return res; -+ } -+ -+ if (ready =3D=3D NRF52_NVMC_READY) -+ return ERROR_OK; -+ -+ alive_sleep(1); -+ } while (timeout--); -+ -+ LOG_DEBUG("Timed out waiting for the NVMC to be ready"); -+ return ERROR_FLASH_BUSY; -+} -+ -+static int nrf52_nvmc_erase_enable(struct nrf52_info *chip) -+{ -+ int res; -+ -+ res =3D nrf52_wait_for_nvmc(chip); -+ if (res !=3D ERROR_OK) -+ return res; -+ -+ res =3D target_write_u32(chip->target, -+ NRF52_NVMC_CONFIG_ADDR, -+ NRF52_NVMC_CONFIG_EEN); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Failed to configure the NVMC for erasing"); -+ return res; -+ } -+ -+ return res; -+} -+ -+static int nrf52_nvmc_write_enable(struct nrf52_info *chip) -+{ -+ int res; -+ -+ res =3D nrf52_wait_for_nvmc(chip); -+ if (res !=3D ERROR_OK) -+ return res; -+ -+ res =3D target_write_u32(chip->target, -+ NRF52_NVMC_CONFIG_ADDR, -+ NRF52_NVMC_CONFIG_WEN); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Failed to configure the NVMC for writing"); -+ return res; -+ } -+ -+ return res; -+} -+ -+static int nrf52_nvmc_read_only(struct nrf52_info *chip) -+{ -+ int res; -+ -+ res =3D nrf52_wait_for_nvmc(chip); -+ if (res !=3D ERROR_OK) -+ return res; -+ -+ res =3D target_write_u32(chip->target, -+ NRF52_NVMC_CONFIG_ADDR, -+ NRF52_NVMC_CONFIG_REN); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Failed to configure the NVMC for read-only"); -+ return res; -+ } -+ -+ return res; -+} -+ -+static int nrf52_nvmc_generic_erase(struct nrf52_info *chip, -+ uint32_t erase_register, -+ uint32_t erase_value) -+{ -+ int res; -+ -+ res =3D nrf52_nvmc_erase_enable(chip); -+ if (res !=3D ERROR_OK) -+ return res; -+ -+ res =3D target_write_u32(chip->target, -+ erase_register, -+ erase_value); -+ if (res !=3D ERROR_OK) -+ LOG_ERROR("Failed to write NVMC erase register"); -+ -+ return nrf52_nvmc_read_only(chip); -+} -+ -+static int nrf52_protect_check(struct flash_bank *bank) -+{ -+ LOG_WARNING("nrf52_protect_check() is not implemented for nRF52 series d= evices yet"); -+ return ERROR_OK; -+} -+ -+static int nrf52_protect(struct flash_bank *bank, int set, int first, int= last) -+{ -+ LOG_WARNING("nrf52_protect() is not implemented for nRF52 series devices= yet"); -+ return ERROR_OK; -+} -+ -+static struct flash_sector *nrf52_find_sector_by_address(struct flash_ban= k *bank, uint32_t address) -+{ -+ struct nrf52_info *chip =3D bank->driver_priv; -+ assert(chip !=3D NULL); -+ -+ for (int i =3D 0; i < bank->num_sectors; i++) -+ if (bank->sectors[i].offset <=3D address && -+ address < (bank->sectors[i].offset + chip->code_page_size)) { -+ return &bank->sectors[i]; -+ } -+ -+ return NULL; -+} -+ -+static int nrf52_erase_all(struct nrf52_info *chip) -+{ -+ LOG_DEBUG("Erasing all non-volatile memory"); -+ return nrf52_nvmc_generic_erase(chip, -+ NRF52_NVMC_ERASEALL_ADDR, -+ 0x01); -+} -+ -+static int nrf52_erase_page(struct flash_bank *bank, -+ struct nrf52_info *chip, -+ struct flash_sector *sector) -+{ -+ int res; -+ -+ LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset); -+ if (sector->is_protected =3D=3D 1) { -+ LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32, sector->offset= ); -+ return ERROR_FAIL; -+ } -+ -+ if (bank->base =3D=3D NRF52_UICR_BASE_ADDR) { -+ res =3D nrf52_nvmc_generic_erase(chip, -+ NRF52_NVMC_ERASEUICR_ADDR, -+ 0x00000001); -+ } else { -+ res =3D nrf52_nvmc_generic_erase(chip, -+ NRF52_NVMC_ERASEPAGE_ADDR, -+ sector->offset); -+ } -+ -+ if (res =3D=3D ERROR_OK) -+ sector->is_erased =3D 1; -+ return res; -+} -+ -+static const uint8_t nrf52_flash_write_code[] =3D { -+ /* See contrib/loaders/flash/cortex-m0.S */ -+ /* : */ -+ 0x0d, 0x68, /* ldr r5, [r1, #0] */ -+ 0x00, 0x2d, /* cmp r5, #0 */ -+ 0x0b, 0xd0, /* beq.n 1e */ -+ 0x4c, 0x68, /* ldr r4, [r1, #4] */ -+ 0xac, 0x42, /* cmp r4, r5 */ -+ 0xf9, 0xd0, /* beq.n 0 */ -+ 0x20, 0xcc, /* ldmia r4!, {r5} */ -+ 0x20, 0xc3, /* stmia r3!, {r5} */ -+ 0x94, 0x42, /* cmp r4, r2 */ -+ 0x01, 0xd3, /* bcc.n 18 */ -+ 0x0c, 0x46, /* mov r4, r1 */ -+ 0x08, 0x34, /* adds r4, #8 */ -+ /* : */ -+ 0x4c, 0x60, /* str r4, [r1, #4] */ -+ 0x04, 0x38, /* subs r0, #4 */ -+ 0xf0, 0xd1, /* bne.n 0 */ -+ /* : */ -+ 0x00, 0xbe /* bkpt 0x0000 */ -+}; -+ -+ -+/* Start a low level flash write for the specified region */ -+static int nrf52_ll_flash_write(struct nrf52_info *chip, uint32_t offset,= const uint8_t *buffer, uint32_t bytes) -+{ -+ struct target *target =3D chip->target; -+ uint32_t buffer_size =3D 8192; -+ struct working_area *write_algorithm; -+ struct working_area *source; -+ uint32_t address =3D NRF52_FLASH_BASE_ADDR + offset; -+ struct reg_param reg_params[4]; -+ struct armv7m_algorithm armv7m_info; -+ int retval =3D ERROR_OK; -+ -+ LOG_DEBUG("Writing buffer to flash offset=3D0x%"PRIx32" bytes=3D0x%"PRIx= 32, offset, bytes); -+ assert(bytes % 4 =3D=3D 0); -+ -+ /* allocate working area with flash programming code */ -+ if (target_alloc_working_area(target, sizeof(nrf52_flash_write_code), -+ &write_algorithm) !=3D ERROR_OK) { -+ LOG_WARNING("no working area available, falling back to slow memory wri= tes"); -+ -+ for (; bytes > 0; bytes -=3D 4) { -+ retval =3D target_write_memory(chip->target, -+ offset, 4, 1, buffer); -+ if (retval !=3D ERROR_OK) -+ return retval; -+ -+ retval =3D nrf52_wait_for_nvmc(chip); -+ if (retval !=3D ERROR_OK) -+ return retval; -+ -+ offset +=3D 4; -+ buffer +=3D 4; -+ } -+ -+ return ERROR_OK; -+ } -+ -+ LOG_WARNING("using fast async flash loader. This is currently supported"= ); -+ LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add"); -+ LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf52.cfg to disable= it"); -+ -+ retval =3D target_write_buffer(target, write_algorithm->address, -+ sizeof(nrf52_flash_write_code), -+ nrf52_flash_write_code); -+ if (retval !=3D ERROR_OK) -+ return retval; -+ -+ /* memory buffer */ -+ while (target_alloc_working_area(target, buffer_size, &source) !=3D ERRO= R_OK) { -+ buffer_size /=3D 2; -+ buffer_size &=3D ~3UL; /* Make sure it's 4 byte aligned */ -+ if (buffer_size <=3D 256) { -+ /* free working area, write algorithm already allocated */ -+ target_free_working_area(target, write_algorithm); -+ -+ LOG_WARNING("No large enough working area available, can't do block me= mory writes"); -+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; -+ } -+ } -+ -+ armv7m_info.common_magic =3D ARMV7M_COMMON_MAGIC; -+ armv7m_info.core_mode =3D ARM_MODE_THREAD; -+ -+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */ -+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer start */ -+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer end */ -+ init_reg_param(®_params[3], "r3", 32, PARAM_IN_OUT); /* target addres= s */ -+ -+ buf_set_u32(reg_params[0].value, 0, 32, bytes); -+ buf_set_u32(reg_params[1].value, 0, 32, source->address); -+ buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size); -+ buf_set_u32(reg_params[3].value, 0, 32, address); -+ -+ retval =3D target_run_flash_async_algorithm(target, buffer, bytes/4, 4, -+ 0, NULL, -+ 4, reg_params, -+ source->address, source->size, -+ write_algorithm->address, 0, -+ &armv7m_info); -+ -+ target_free_working_area(target, source); -+ target_free_working_area(target, write_algorithm); -+ -+ destroy_reg_param(®_params[0]); -+ destroy_reg_param(®_params[1]); -+ destroy_reg_param(®_params[2]); -+ destroy_reg_param(®_params[3]); -+ -+ return retval; -+} -+ -+/* Check and erase flash sectors in specified range, then start a low lev= el page write. -+ start/end must be sector aligned. -+*/ -+static int nrf52_write_pages(struct flash_bank *bank, uint32_t start, uin= t32_t end, const uint8_t *buffer) -+{ -+ int res; -+ uint32_t offset; -+ struct flash_sector *sector; -+ struct nrf52_info *chip =3D bank->driver_priv; -+ assert(chip !=3D NULL); -+ -+ assert(start % chip->code_page_size =3D=3D 0); -+ assert(end % chip->code_page_size =3D=3D 0); -+ -+ /* Erase all sectors */ -+ for (offset =3D start; offset < end; offset +=3D chip->code_page_size) { -+ sector =3D nrf52_find_sector_by_address(bank, offset); -+ -+ if (sector =3D=3D NULL) { -+ LOG_ERROR("Invalid sector @ 0x%08"PRIx32, offset); -+ return ERROR_FLASH_SECTOR_INVALID; -+ } -+ -+ if (sector->is_protected =3D=3D 1) { -+ LOG_ERROR("Can't erase protected sector @ 0x%08"PRIx32, offset); -+ return ERROR_FAIL; -+ } -+ -+ if (sector->is_erased !=3D 1) { /* 1 =3D erased, 0=3D not erased, -1 = =3D unknown */ -+ res =3D nrf52_erase_page(bank, chip, sector); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset); -+ return res; -+ } -+ } -+ sector->is_erased =3D 1; -+ } -+ -+ res =3D nrf52_nvmc_write_enable(chip); -+ if (res !=3D ERROR_OK) -+ return res; -+ -+ res =3D nrf52_ll_flash_write(chip, start, buffer, (end - start)); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Failed to write FLASH"); -+ nrf52_nvmc_read_only(chip); -+ return res; -+ } -+ -+ return nrf52_nvmc_read_only(chip); -+} -+ -+static int nrf52_erase(struct flash_bank *bank, int first, int last) -+{ -+ int res =3D ERROR_OK; -+ struct nrf52_info *chip =3D bank->driver_priv; -+ assert(chip !=3D NULL); -+ -+ /* For each sector to be erased */ -+ for (int s =3D first; s <=3D last && res =3D=3D ERROR_OK; s++) -+ res =3D nrf52_erase_page(bank, chip, &bank->sectors[s]); -+ -+ return res; -+} -+ -+static int nrf52_code_flash_write(struct flash_bank *bank, -+ struct nrf52_info *chip, -+ const uint8_t *buffer, uint32_t offset, uint32_t count) -+{ -+ int res; -+ /* Need to perform reads to fill any gaps we need to preserve in the fir= st page, -+ before the start of buffer, or in the last page, after the end of buf= fer */ -+ uint32_t first_page =3D offset / chip->code_page_size; -+ uint32_t last_page =3D DIV_ROUND_UP(offset+count, chip->code_page_size); -+ -+ uint32_t first_page_offset =3D first_page * chip->code_page_size; -+ uint32_t last_page_offset =3D last_page * chip->code_page_size; -+ -+ LOG_DEBUG("Padding write from 0x%08"PRIx32"-0x%08"PRIx32" as 0x%08"PRIx3= 2"-0x%08"PRIx32, -+ offset, offset+count, first_page_offset, last_page_offset); -+ -+ uint32_t page_cnt =3D last_page - first_page; -+ uint8_t buffer_to_flash[page_cnt * chip->code_page_size]; -+ -+ /* Fill in any space between start of first page and start of buffer */ -+ uint32_t pre =3D offset - first_page_offset; -+ if (pre > 0) { -+ res =3D target_read_memory(bank->target, first_page_offset, 1, pre, buf= fer_to_flash); -+ if (res !=3D ERROR_OK) -+ return res; -+ } -+ -+ /* Fill in main contents of buffer */ -+ memcpy(buffer_to_flash + pre, buffer, count); -+ -+ /* Fill in any space between end of buffer and end of last page */ -+ uint32_t post =3D last_page_offset - (offset + count); -+ if (post > 0) { -+ /* Retrieve the full row contents from Flash */ -+ res =3D target_read_memory(bank->target, offset + count, 1, post, buffe= r_to_flash + pre + count); -+ if (res !=3D ERROR_OK) -+ return res; -+ } -+ -+ return nrf52_write_pages(bank, first_page_offset, last_page_offset, buff= er_to_flash); -+} -+ -+static int nrf52_uicr_flash_write(struct flash_bank *bank, -+ struct nrf52_info *chip, -+ const uint8_t *buffer, uint32_t offset, uint32_t count) -+{ -+ int res; -+ uint32_t nrf52_uicr_size =3D chip->code_page_size; -+ uint8_t uicr[nrf52_uicr_size]; -+ struct flash_sector *sector =3D &bank->sectors[0]; -+ -+ if ((offset + count) > nrf52_uicr_size) -+ return ERROR_FAIL; -+ -+ res =3D target_read_memory(bank->target, NRF52_UICR_BASE_ADDR, 1, nrf52_= uicr_size, uicr); -+ -+ if (res !=3D ERROR_OK) -+ return res; -+ -+ if (sector->is_erased !=3D 1) { -+ res =3D nrf52_erase_page(bank, chip, sector); -+ if (res !=3D ERROR_OK) -+ return res; -+ } -+ -+ memcpy(&uicr[offset], buffer, count); -+ -+ res =3D nrf52_nvmc_write_enable(chip); -+ if (res !=3D ERROR_OK) -+ return res; -+ -+ res =3D nrf52_ll_flash_write(chip, NRF52_UICR_BASE_ADDR, uicr, nrf52_uic= r_size); -+ if (res !=3D ERROR_OK) { -+ nrf52_nvmc_read_only(chip); -+ return res; -+ } -+ -+ return nrf52_nvmc_read_only(chip); -+} -+ -+ -+static int nrf52_write(struct flash_bank *bank, const uint8_t *buffer, -+ uint32_t offset, uint32_t count) -+{ -+ struct nrf52_info *chip =3D bank->driver_priv; -+ assert(chip !=3D NULL); -+ -+ return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, c= ount); -+} -+ -+ -+FLASH_BANK_COMMAND_HANDLER(nrf52_flash_bank_command) -+{ -+ static struct nrf52_info *chip; -+ -+ assert(bank !=3D NULL); -+ -+ switch (bank->base) { -+ case NRF52_FLASH_BASE_ADDR: -+ bank->bank_number =3D 0; -+ break; -+ case NRF52_UICR_BASE_ADDR: -+ bank->bank_number =3D 1; -+ break; -+ default: -+ LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base); -+ return ERROR_FAIL; -+ } -+ -+ if (!chip) { -+ /* Create a new chip */ -+ chip =3D calloc(1, sizeof(*chip)); -+ assert(chip !=3D NULL); -+ -+ chip->target =3D bank->target; -+ } -+ -+ switch (bank->base) { -+ case NRF52_FLASH_BASE_ADDR: -+ chip->bank[bank->bank_number].write =3D nrf52_code_flash_write; -+ break; -+ case NRF52_UICR_BASE_ADDR: -+ chip->bank[bank->bank_number].write =3D nrf52_uicr_flash_write; -+ break; -+ } -+ -+ chip->bank[bank->bank_number].probed =3D false; -+ bank->driver_priv =3D chip; -+ -+ return ERROR_OK; -+} -+ -+COMMAND_HANDLER(nrf52_handle_mass_erase_command) -+{ -+ int res; -+ struct flash_bank *bank =3D NULL; -+ struct target *target =3D get_current_target(CMD_CTX); -+ -+ res =3D get_flash_bank_by_addr(target, NRF52_FLASH_BASE_ADDR, true, &ban= k); -+ if (res !=3D ERROR_OK) -+ return res; -+ -+ assert(bank !=3D NULL); -+ -+ struct nrf52_info *chip =3D bank->driver_priv; -+ assert(chip !=3D NULL); -+ -+ res =3D nrf52_erase_all(chip); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Failed to erase the chip"); -+ nrf52_protect_check(bank); -+ return res; -+ } -+ -+ for (int i =3D 0; i < bank->num_sectors; i++) -+ bank->sectors[i].is_erased =3D 1; -+ -+ res =3D nrf52_protect_check(bank); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Failed to check chip's write protection"); -+ return res; -+ } -+ -+ res =3D get_flash_bank_by_addr(target, NRF52_UICR_BASE_ADDR, true, &bank= ); -+ if (res !=3D ERROR_OK) -+ return res; -+ -+ bank->sectors[0].is_erased =3D 1; -+ -+ return ERROR_OK; -+} -+ -+static int nrf52_info(struct flash_bank *bank, char *buf, int buf_size) -+{ -+ int res; -+ uint32_t ficr[2]; -+ struct nrf52_info *chip =3D bank->driver_priv; -+ assert(chip !=3D NULL); -+ -+ res =3D target_read_u32(chip->target, NRF52_FICR_CODEPAGESIZE_ADDR, &fic= r[0]); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Couldn't read NVMC_READY register"); -+ return res; -+ } -+ -+ res =3D target_read_u32(chip->target, NRF52_FICR_CODESIZE_ADDR, &ficr[1]= ); -+ if (res !=3D ERROR_OK) { -+ LOG_ERROR("Couldn't read NVMC_READY register"); -+ return res; -+ } -+ -+ snprintf(buf, buf_size, -+ "\n--------nRF52 Series Device--------\n\n" -+ "\n[factory information control block]\n" -+ "code page size: %"PRIu32"B\n" -+ "code memory size: %"PRIu32"kB\n", -+ ficr[0], -+ (ficr[1] * ficr[0]) / 1024); -+ -+ return ERROR_OK; -+} -+ -+static const struct command_registration nrf52_exec_command_handlers[] = =3D { -+ { -+ .name =3D "mass_erase", -+ .handler =3D nrf52_handle_mass_erase_command, -+ .mode =3D COMMAND_EXEC, -+ .help =3D "Erase all flash contents of the chip.", -+ }, -+ COMMAND_REGISTRATION_DONE -+}; -+ -+static const struct command_registration nrf52_command_handlers[] =3D { -+ { -+ .name =3D "nrf52", -+ .mode =3D COMMAND_ANY, -+ .help =3D "nrf52 flash command group", -+ .usage =3D "", -+ .chain =3D nrf52_exec_command_handlers, -+ }, -+ COMMAND_REGISTRATION_DONE -+}; -+ -+struct flash_driver nrf52_flash =3D { -+ .name =3D "nrf52", -+ .commands =3D nrf52_command_handlers, -+ .flash_bank_command =3D nrf52_flash_bank_command, -+ .info =3D nrf52_info, -+ .erase =3D nrf52_erase, -+ .protect =3D nrf52_protect, -+ .write =3D nrf52_write, -+ .read =3D default_flash_read, -+ .probe =3D nrf52_probe, -+ .auto_probe =3D nrf52_auto_probe, -+ .erase_check =3D default_flash_blank_check, -+ .protect_check =3D nrf52_protect_check, -+}; -diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg -index c1cbf1a..41a22ff 100644 ---- a/tcl/target/nrf52.cfg -+++ b/tcl/target/nrf52.cfg -@@ -10,6 +10,13 @@ if { [info exists CHIPNAME] } { - set _CHIPNAME nrf52 - } -=20 -+# Work-area is a space in RAM used for flash programming, by default use = 16kB. -+if { [info exists WORKAREASIZE] } { -+ set _WORKAREASIZE $WORKAREASIZE -+} else { -+ set _WORKAREASIZE 0x4000 -+} -+ - if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID - } else { -@@ -22,7 +29,15 @@ set _TARGETNAME $_CHIPNAME.cpu - target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME -=20 - adapter_khz 10000 -+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKA= REASIZE -work-area-backup 0 -=20 - if { ![using_hla] } { - cortex_m reset_config sysresetreq - } -+ -+flash bank $_CHIPNAME.flash nrf52 0x00000000 0 1 1 $_TARGETNAME -+flash bank $_CHIPNAME.uicr nrf52 0x10001000 0 1 1 $_TARGETNAME -+ -+adapter_khz 1000 -+ -+$_TARGETNAME configure -event reset-end {} --=20 2.28.0 --=-=-=--