[bug#73918] [PATCH v1 1/2] gnu: iverilog: Fix yosys tests

[bug#73918] [PATCH v1 1/2] gnu: iverilog: Fix yosys tests

[Jakob Kirsch via Guix-patches via]

* gnu/packages/fpga.scm (iverilog): [inputs]: Add zlib.

Change-Id: I961bf73b17f96a5891232a8646bc04581dfb8bfc
---
 gnu/packages/fpga.scm | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 545ec3482d..153d17d1f3 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -125,6 +125,7 @@ (define-public iverilog
       #:make-flags #~(list (string-append "PREFIX="
                                           #$output))
       #:bootstrap-scripts #~(list "autoconf.sh")))
+    (inputs (list zlib))
     (native-inputs (list autoconf bison flex gperf))
     (home-page "https://steveicarus.github.io/iverilog")
     (synopsis "FPGA Verilog simulation and synthesis tool")

base-commit: 5703914e93d81ac6037240582abe899282e78f15
--
2.46.0

[bug#73918] [PATCH v2 1/2] gnu: iverilog: Fix yosys tests

[Jakob Kirsch via Guix-patches via]

* gnu/packages/fpga.scm (iverilog): [inputs]: Add zlib.

Change-Id: I961bf73b17f96a5891232a8646bc04581dfb8bfc
---
 gnu/packages/fpga.scm | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 545ec3482d..153d17d1f3 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -125,6 +125,7 @@ (define-public iverilog
       #:make-flags #~(list (string-append "PREFIX="
                                           #$output))
       #:bootstrap-scripts #~(list "autoconf.sh")))
+    (inputs (list zlib))
     (native-inputs (list autoconf bison flex gperf))
     (home-page "https://steveicarus.github.io/iverilog")
     (synopsis "FPGA Verilog simulation and synthesis tool")

base-commit: 5703914e93d81ac6037240582abe899282e78f15
--
2.46.0

[bug#73918] [PATCH v2 2/2] gnu: yosys: Update to 0.46.

[Jakob Kirsch via Guix-patches via]

* gnu/packages/fpga.scm (yosys): Update to 0.46.

Change-Id: Ibdd4c02155ace62bf50ff9b7bb605edc21698c2a
---
 gnu/packages/fpga.scm | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 153d17d1f3..83e81bfc50 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -8,6 +8,7 @@
 ;;; Copyright © 2022 Christian Gelinek <cgelinek@radlogic.com.au>
 ;;; Copyright © 2022 jgart <jgart@dismail.de>
 ;;; Copyright © 2024 Efraim Flashner <efraim@flashner.co.il>
+;;; Copyright © 2024 Jakob Kirsch <jakob.kirsch@web.de>
 ;;;
 ;;; This file is part of GNU Guix.
 ;;;
@@ -149,15 +150,15 @@ (define-public iverilog
 (define-public yosys
   (package
     (name "yosys")
-    (version "0.26")
+    (version "0.46")
     (source (origin
               (method git-fetch)
               (uri (git-reference
                     (url "https://github.com/YosysHQ/yosys")
-                    (commit (string-append "yosys-" version))))
+                    (commit version)))
               (sha256
                (base32
-                "0s79ljgbcfkm7l9km7dcvlz4mnx38nbyxppscvh5il5lw07n45gx"))
+                "1zj7vbpy6v1wn4p5cjs4hdjd467a1j1aj2qhs148bl2s6mzq3p86"))
               (file-name (git-file-name name version))))
     (build-system gnu-build-system)
     (arguments
--
2.46.0