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From: Jakob Kirsch via Guix-patches via <guix-patches@gnu.org>
To: 73918@debbugs.gnu.org
Cc: Jakob Kirsch <jakob.kirsch@web.de>
Subject: [bug#73918] [PATCH v1 1/2] gnu: iverilog: Fix yosys tests
Date: Sun, 20 Oct 2024 23:39:44 +0200	[thread overview]
Message-ID: <4da104f41f60809288973a250f258ddb724616c3.1729460353.git.jakob.kirsch@web.de> (raw)

* gnu/packages/fpga.scm (iverilog): [inputs]: Add zlib.

Change-Id: I961bf73b17f96a5891232a8646bc04581dfb8bfc
---
 gnu/packages/fpga.scm | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 545ec3482d..153d17d1f3 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -125,6 +125,7 @@ (define-public iverilog
       #:make-flags #~(list (string-append "PREFIX="
                                           #$output))
       #:bootstrap-scripts #~(list "autoconf.sh")))
+    (inputs (list zlib))
     (native-inputs (list autoconf bison flex gperf))
     (home-page "https://steveicarus.github.io/iverilog")
     (synopsis "FPGA Verilog simulation and synthesis tool")

base-commit: 5703914e93d81ac6037240582abe899282e78f15
--
2.46.0





             reply	other threads:[~2024-10-20 21:41 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-20 21:39 Jakob Kirsch via Guix-patches via [this message]
2024-10-20 21:47 ` [bug#73918] [PATCH v2 1/2] gnu: iverilog: Fix yosys tests Jakob Kirsch via Guix-patches via
2024-10-20 21:48   ` [bug#73918] [PATCH v2 2/2] gnu: yosys: Update to 0.46 Jakob Kirsch via Guix-patches via

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