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* [bug#68791] [PATCH 0/3] Patch series to add/update nextpnr-ecp5 + deps
@ 2024-01-29  4:27 Gary Wong
  2024-01-29 15:01 ` [bug#68791] [PATCH 1/3] gnu: yosys: Update to 0.37 Gary Wong
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Gary Wong @ 2024-01-29  4:27 UTC (permalink / raw)
  To: 68791

Thank you very much for all your Guix work.  Please consider
this series of patches to (gnu packages fpga), adding the
nextpnr-ecp5 package and updating the related yosys version.

(Please note that the yosys patch appears bigger than strictly
necessary, since I applied 'guix style' as recommended in
Section 22.6 of the manual.  I can submit a smaller patch
retaining the old formatting if that would be preferable.)

Many thanks,
Gary.

Gary Wong (3):
  gnu: yosys: Update to 0.37.
  gnu: Add trellis.
  gnu: Add nextpnr-ecp5.

 gnu/packages/fpga.scm | 221 ++++++++++++++++++++++++++++--------------
 1 file changed, 147 insertions(+), 74 deletions(-)


base-commit: 65dc2d40cb113382fb98796f1d04099f28cab355
-- 
2.41.0





^ permalink raw reply	[flat|nested] 5+ messages in thread

* [bug#68791] [PATCH 1/3] gnu: yosys: Update to 0.37.
  2024-01-29  4:27 [bug#68791] [PATCH 0/3] Patch series to add/update nextpnr-ecp5 + deps Gary Wong
@ 2024-01-29 15:01 ` Gary Wong
  2024-01-29 15:03 ` [bug#68791] [PATCH 2/3] gnu: Add trellis Gary Wong
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Gary Wong @ 2024-01-29 15:01 UTC (permalink / raw)
  To: 68791

* gnu/packages/fpga.scm (yosys): Update to 0.37, and
disable fragile iverilog invocation in arch/run-test.sh.

Change-Id: Ie9ed39ac47fb0a3dde1acd5f699724dc709a00a0
---
 gnu/packages/fpga.scm | 162 +++++++++++++++++++++++-------------------
 1 file changed, 88 insertions(+), 74 deletions(-)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 13ac1a0b..99841fb6 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -7,6 +7,7 @@
 ;;; Copyright © 2021 Andrew Miloradovsky <andrew@interpretmath.pw>
 ;;; Copyright © 2022 Christian Gelinek <cgelinek@radlogic.com.au>
 ;;; Copyright © 2022 jgart <jgart@dismail.de>
+;;; Copyright © 2024 Gary Wong <gtw@gnu.org>
 ;;;
 ;;; This file is part of GNU Guix.
 ;;;
@@ -137,84 +138,97 @@ (define-public iverilog
 (define-public yosys
   (package
     (name "yosys")
-    (version "0.26")
-    (source (origin
-              (method git-fetch)
-              (uri (git-reference
-                    (url "https://github.com/YosysHQ/yosys")
-                    (commit (string-append "yosys-" version))))
-              (sha256
-               (base32
-                "0s79ljgbcfkm7l9km7dcvlz4mnx38nbyxppscvh5il5lw07n45gx"))
-              (file-name (git-file-name name version))))
+    (version "0.37")
+    (source
+     (origin
+       (method git-fetch)
+       (uri (git-reference
+             (url "https://github.com/YosysHQ/yosys")
+             (commit (string-append "yosys-" version))))
+       (sha256
+        (base32 "13f8d02n7fibf77nwfqqlbzfwrpc5qcjx059v04cb76vk9k4bkqp"))
+       (file-name (git-file-name name version))))
     (build-system gnu-build-system)
     (arguments
      (list
       #:test-target "test"
-      #:make-flags #~(list "CC=gcc"
-                           "CXX=g++"
-                           (string-append "PREFIX=" #$output))
-      #:phases
-      #~(modify-phases %standard-phases
-          (add-before 'configure 'fix-paths
-            (lambda* (#:key inputs #:allow-other-keys)
-              (substitute* "./backends/smt2/smtio.py"
-                (("\\['z3")
-                 (string-append "['" (search-input-file inputs "/bin/z3"))))
-              (substitute* "./kernel/fstdata.cc"
-                (("vcd2fst")
-                 (search-input-file inputs "/bin/vcd2fst")))
-              (substitute* '("./passes/cmds/show.cc"
-                             "./passes/cmds/viz.cc")
-                (("exec xdot")
-                 (string-append "exec " (search-input-file inputs
-                                                           "/bin/xdot")))
-                (("dot -")
-                 (string-append (search-input-file inputs "/bin/dot") " -"))
-                (("fuser")
-                 (search-input-file inputs "/bin/fuser")))))
-          (replace 'configure
-            (lambda* (#:key make-flags #:allow-other-keys)
-              (apply invoke "make" "config-gcc" make-flags)))
-          (add-after 'configure 'use-external-abc
-            (lambda* (#:key inputs #:allow-other-keys)
-              (substitute* '("./Makefile")
-                (("ABCEXTERNAL \\?=")
-                 (string-append "ABCEXTERNAL = "
-                                (search-input-file inputs "/bin/abc"))))))
-          (add-after 'install 'add-symbolic-link
-            (lambda* (#:key inputs #:allow-other-keys)
-              ;; Previously this package provided a copy of the "abc"
-              ;; executable in its output, named "yosys-abc".  Create a
-              ;; symbolic link so any external uses of that name continue to
-              ;; work.
-              (symlink (search-input-file inputs "/bin/abc")
-                       (string-append #$output "/bin/yosys-abc"))))
-          (add-after 'install 'wrap
-            (lambda* (#:key inputs #:allow-other-keys)
-              (wrap-program (string-append #$output "/bin/yosys-witness")
-                `("GUIX_PYTHONPATH" ":" prefix (,(getenv "GUIX_PYTHONPATH")))))))))
-    (native-inputs
-     (list bison
-           flex
-           gawk ; for the tests and "make" progress pretty-printing
-           iverilog ; for the tests
-           pkg-config
-           python
-           tcl)) ; tclsh for the tests
-    (inputs
-     (list abc
-           graphviz
-           gtkwave
-           libffi
-           psmisc
-           readline
-           tcl
-           xdot
-           z3
-           zlib
-           python
-           python-click))
+      #:make-flags #~(list "CC=gcc" "CXX=g++"
+                           (string-append "PREFIX="
+                                          #$output))
+      #:phases #~(modify-phases %standard-phases
+                   (add-before 'configure 'fix-paths
+                     (lambda* (#:key inputs #:allow-other-keys)
+                       (substitute* "./backends/smt2/smtio.py"
+                         (("\\['z3")
+                          (string-append "['"
+                                         (search-input-file inputs "/bin/z3"))))
+                       (substitute* "./kernel/fstdata.cc"
+                         (("vcd2fst")
+                          (search-input-file inputs "/bin/vcd2fst")))
+                       (substitute* '("./passes/cmds/show.cc"
+                                      "./passes/cmds/viz.cc")
+                         (("exec xdot")
+                          (string-append "exec "
+                                         (search-input-file inputs "/bin/xdot")))
+                         (("dot -")
+                          (string-append (search-input-file inputs "/bin/dot")
+                                         " -"))
+                         (("fuser")
+                          (search-input-file inputs "/bin/fuser")))))
+                   (add-before 'configure 'fix-tests
+                     (lambda* (#:key inputs #:allow-other-keys)
+                       ;; The arch/run-test.sh script performs a syntax check
+                       ;; on the included simulation models, by running
+                       ;; iverilog over the model source.  Unfortunately this
+                       ;; test is prone to false positives, because it is
+                       ;; highly sensitive to the version of iverilog in use.
+                       ;; Disable iverilog invocation for this test.
+                       (substitute* '("./tests/arch/run-test.sh")
+                         (("iverilog")
+                          "# iverilog"))))
+                   (replace 'configure
+                     (lambda* (#:key make-flags #:allow-other-keys)
+                       (apply invoke "make" "config-gcc" make-flags)))
+                   (add-after 'configure 'use-external-abc
+                     (lambda* (#:key inputs #:allow-other-keys)
+                       (substitute* '("./Makefile")
+                         (("ABCEXTERNAL \\?=")
+                          (string-append "ABCEXTERNAL = "
+                                         (search-input-file inputs "/bin/abc"))))))
+                   (add-after 'install 'add-symbolic-link
+                     (lambda* (#:key inputs #:allow-other-keys)
+                       ;; Previously this package provided a copy of the "abc"
+                       ;; executable in its output, named "yosys-abc".  Create
+                       ;; a symbolic link so any external uses of that name
+                       ;; continue to work.
+                       (symlink (search-input-file inputs "/bin/abc")
+                                (string-append #$output "/bin/yosys-abc"))))
+                   (add-after 'install 'wrap
+                     (lambda* (#:key inputs #:allow-other-keys)
+                       (wrap-program (string-append #$output
+                                                    "/bin/yosys-witness")
+                         `("GUIX_PYTHONPATH" ":" prefix
+                           (,(getenv "GUIX_PYTHONPATH")))))))))
+    (native-inputs (list bison
+                         flex
+                         gawk ;for the tests and "make" progress pretty-printing
+                         iverilog ;for the tests
+                         pkg-config
+                         python
+                         tcl)) ;tclsh for the tests
+    (inputs (list abc
+                  bash-minimal
+                  graphviz
+                  gtkwave
+                  libffi
+                  psmisc
+                  readline
+                  tcl
+                  xdot
+                  z3
+                  zlib
+                  python
+                  python-click))
     (home-page "https://yosyshq.net/yosys/")
     (synopsis "FPGA Verilog RTL synthesizer")
     (description "Yosys synthesizes Verilog-2005.")
-- 
2.41.0





^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [bug#68791] [PATCH 2/3] gnu: Add trellis.
  2024-01-29  4:27 [bug#68791] [PATCH 0/3] Patch series to add/update nextpnr-ecp5 + deps Gary Wong
  2024-01-29 15:01 ` [bug#68791] [PATCH 1/3] gnu: yosys: Update to 0.37 Gary Wong
@ 2024-01-29 15:03 ` Gary Wong
  2024-01-29 15:03 ` [bug#68791] [PATCH 3/3] gnu: Add nextpnr-ecp5 Gary Wong
  2024-03-23 14:39 ` [bug#68791] [PATCH 0/3] Patch series to add/update nextpnr-ecp5 + deps Gary Wong
  3 siblings, 0 replies; 5+ messages in thread
From: Gary Wong @ 2024-01-29 15:03 UTC (permalink / raw)
  To: 68791

* gnu/packages/fpga.scm (trellis): New variable.

Change-Id: I90a7c7c0994508a16193c5ae2b8659c1d32a3c33
---
 gnu/packages/fpga.scm | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 99841fb6..b42a3503 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -619,3 +619,36 @@ (define-public openfpgaloader
 to an FPGA.")
     (home-page "https://f4pga.org/")
     (license license:asl2.0)))
+
+(define-public trellis
+  (package
+    (name "trellis")
+    (version "1.4")
+    (source
+     (origin
+       (method git-fetch)
+       (uri (git-reference
+             (url "https://github.com/YosysHQ/prjtrellis")
+             (commit version)
+             (recursive? #t))) ;for the database submodule
+       (file-name (git-file-name name version))
+       (sha256
+        (base32 "0c3asdfrjmnc6q3vawn3nfghgg43iajwy2zb8kck9d3wrypbhlmc"))))
+    (inputs (list boost python))
+    (build-system cmake-build-system)
+    (arguments
+     (list
+      #:out-of-source? #f ;README: "unsupported when coupled with nextpnr"
+      #:tests? #f ;contains no test target
+      #:phases #~(modify-phases %standard-phases
+                   (add-before 'configure 'chdir-libtrellis
+                     (lambda* (#:key #:allow-other-keys)
+                       (chdir "libtrellis"))))))
+    (synopsis "Lattice ECP5 bitstream processing")
+    (description
+     "Project Trellis enables a fully open-source flow for ECP5
+FPGAs using Yosys for Verilog synthesis and nextpnr for place and
+route.  Project Trellis itself provides the device database and tools
+for bitstream creation.")
+    (license (list license:isc license:expat))
+    (home-page "https://github.com/YosysHQ/prjtrellis")))
-- 
2.41.0





^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [bug#68791] [PATCH 3/3] gnu: Add nextpnr-ecp5.
  2024-01-29  4:27 [bug#68791] [PATCH 0/3] Patch series to add/update nextpnr-ecp5 + deps Gary Wong
  2024-01-29 15:01 ` [bug#68791] [PATCH 1/3] gnu: yosys: Update to 0.37 Gary Wong
  2024-01-29 15:03 ` [bug#68791] [PATCH 2/3] gnu: Add trellis Gary Wong
@ 2024-01-29 15:03 ` Gary Wong
  2024-03-23 14:39 ` [bug#68791] [PATCH 0/3] Patch series to add/update nextpnr-ecp5 + deps Gary Wong
  3 siblings, 0 replies; 5+ messages in thread
From: Gary Wong @ 2024-01-29 15:03 UTC (permalink / raw)
  To: 68791

* gnu/packages/fpga.scm (nextpnr-ecp5): New variable.

Change-Id: Iec50903140fc9f0458423adbbe333e189e601922
---
 gnu/packages/fpga.scm | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index b42a3503..3dcd981e 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -652,3 +652,29 @@ (define-public trellis
 for bitstream creation.")
     (license (list license:isc license:expat))
     (home-page "https://github.com/YosysHQ/prjtrellis")))
+
+(define-public nextpnr-ecp5
+  (package
+    (name "nextpnr-ecp5")
+    (version "0.7")
+    (source
+     (origin
+       (method git-fetch)
+       (uri (git-reference
+             (url "https://github.com/YosysHQ/nextpnr")
+             (commit (string-append "nextpnr-" version))))
+       (file-name (git-file-name name version))
+       (sha256
+        (base32 "146nc05ypsyjnxdpayc4g6d16f5igry46nydrb13niix51q11030"))))
+    (inputs (list boost eigen python trellis))
+    (build-system cmake-build-system)
+    (arguments
+     `(#:configure-flags `("-DARCH=ecp5" ,(string-append
+                                           "-DTRELLIS_INSTALL_PREFIX="
+                                           (assoc-ref %build-inputs "trellis")))
+       #:tests? #f)) ;contains no test target
+    (synopsis "Portable FPGA place and route tool")
+    (description "Nextpnr aims to be a vendor neutral, timing driven,
+FOSS FPGA place and route tool.")
+    (home-page "https://github.com/YosysHQ/nextpnr")
+    (license license:isc)))
-- 
2.41.0





^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [bug#68791] [PATCH 0/3] Patch series to add/update nextpnr-ecp5 + deps
  2024-01-29  4:27 [bug#68791] [PATCH 0/3] Patch series to add/update nextpnr-ecp5 + deps Gary Wong
                   ` (2 preceding siblings ...)
  2024-01-29 15:03 ` [bug#68791] [PATCH 3/3] gnu: Add nextpnr-ecp5 Gary Wong
@ 2024-03-23 14:39 ` Gary Wong
  3 siblings, 0 replies; 5+ messages in thread
From: Gary Wong @ 2024-03-23 14:39 UTC (permalink / raw)
  To: 68791

On Sun, Jan 28, 2024 at 09:27:36PM -0700, Gary Wong wrote:
> Thank you very much for all your Guix work.  Please consider
> this series of patches to (gnu packages fpga), adding the
> nextpnr-ecp5 package and updating the related yosys version.

Any thoughts on this?

Thanks very much,
Gary.
-- 
     Gary Wong         gtw@gnu.org         http://www.cs.utah.edu/~gtw/




^ permalink raw reply	[flat|nested] 5+ messages in thread

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2024-01-29 15:03 ` [bug#68791] [PATCH 2/3] gnu: Add trellis Gary Wong
2024-01-29 15:03 ` [bug#68791] [PATCH 3/3] gnu: Add nextpnr-ecp5 Gary Wong
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