From mboxrd@z Thu Jan 1 00:00:00 1970 From: Danny Milosavljevic Subject: [PATCH v2 3/6] gnu: fpga: Add iverilog. Date: Tue, 16 Aug 2016 20:06:50 +0200 Message-ID: <20160816180653.22524-4-dannym@scratchpost.org> References: <20160816180653.22524-1-dannym@scratchpost.org> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.9.1" Return-path: Received: from eggs.gnu.org ([2001:4830:134:3::10]:38224) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bZilp-0002Jy-0J for guix-devel@gnu.org; Tue, 16 Aug 2016 14:07:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bZiln-0007xc-SB for guix-devel@gnu.org; Tue, 16 Aug 2016 14:07:24 -0400 Received: from dd1012.kasserver.com ([85.13.128.8]:43546) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bZiln-0007xT-L0 for guix-devel@gnu.org; Tue, 16 Aug 2016 14:07:23 -0400 In-Reply-To: <20160816180653.22524-1-dannym@scratchpost.org> List-Id: "Development of GNU Guix and the GNU System distribution." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: guix-devel-bounces+gcggd-guix-devel=m.gmane.org@gnu.org Sender: "Guix-devel" To: guix-devel@gnu.org This is a multi-part message in MIME format. --------------2.9.1 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: quoted-printable * gnu/packages/fpga.scm (iverilog): New variable. --- gnu/packages/fpga.scm | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) --------------2.9.1 Content-Type: text/x-patch; name="0003-gnu-fpga-Add-iverilog.patch" Content-Disposition: attachment; filename="0003-gnu-fpga-Add-iverilog.patch" Content-Transfer-Encoding: quoted-printable diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index 7571f87..b0d4819 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -81,3 +81,30 @@ and formal verification.") ;; FIXME use license: MIT Modern variant as described in: ;; (license license:expat)))) + +(define-public iverilog + (package + (name "iverilog") + (version "10.1.1") + (source (origin + (method url-fetch) + (uri + (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/= verilog-" version ".tar.gz")) + (sha256 + (base32 + "1nnassxvq30rnn0r2p85rkb2zwxk97p109y13x3vr365wzgpbapx= ")))) + (build-system gnu-build-system) + (native-inputs + `(("flex" ,flex) + ("bison" ,bison) + ("ghostscript" ,ghostscript) #| ps2pdf |#)) + (home-page "http://iverilog.icarus.com/") + (synopsis "FPGA Verilog Simulation and Synthesis Tool") + (description "Icarus Verilog is a Verilog simulation and synthesis t= ool. +It operates as a compiler, compiling source code written in Verilog +(IEEE-1364) into some target format. +For batch simulation, the compiler can generate an intermediate form cal= led +vvp assembly. +This intermediate form is executed by the ``vvp'' command. +For synthesis, the compiler generates netlists in the desired format.") + (license license:gpl2))) --------------2.9.1--