1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
| | ;;; GNU Guix --- Functional package management for GNU
;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org>
;;;
;;; This file is part of GNU Guix.
;;;
;;; GNU Guix is free software; you can redistribute it and/or modify it
;;; under the terms of the GNU General Public License as published by
;;; the Free Software Foundation; either version 3 of the License, or (at
;;; your option) any later version.
;;;
;;; GNU Guix is distributed in the hope that it will be useful, but
;;; WITHOUT ANY WARRANTY; without even the implied warranty of
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;;; GNU General Public License for more details.
;;;
;;; You should have received a copy of the GNU General Public License
;;; along with GNU Guix. If not, see <http://www.gnu.org/licenses/>.
(define-module (gnu packages fpga)
#:use-module ((guix licenses) #:prefix license:)
#:use-module (guix packages)
#:use-module (guix download)
#:use-module (guix git-download)
#:use-module (guix build-system gnu)
#:use-module (guix build-system cmake)
#:use-module (gnu packages)
#:use-module (gnu packages pkg-config)
#:use-module (gnu packages tcl)
#:use-module (gnu packages readline)
#:use-module (gnu packages python)
#:use-module (gnu packages bison)
#:use-module (gnu packages flex)
#:use-module (gnu packages libffi)
#:use-module (gnu packages zip)
#:use-module (gnu packages perl)
#:use-module (gnu packages ghostscript)
#:use-module (gnu packages gawk)
#:use-module (gnu packages version-control)
#:use-module (gnu packages libftdi))
;; To compile as C code (default):
;; make sure that CC=gcc and ABC_NAMESPACE is not defined.
;; To compile as C++ code with namespaces:
;; make sure that CC=g++ and ABC_NAMESPACE is set to the namespace.
;; For example, add -DABC_NAMESPACE=xxx to OPTFLAGS.
(define-public abc
(let ((commit "5ae4b975c49c"))
(package
(name "abc")
(version (string-append "0.0-" (string-take commit 7)))
(source (origin
(method url-fetch)
(uri
(string-append "https://bitbucket.org/alanmi/abc/get/"
commit ".zip"))
(file-name (string-append name "-" version "-checkout.zip"))
(sha256
(base32
"1syygi1x40rdryih3galr4q8yg1w5bvdzl75hd27v1xq0l5bz3d0"))))
(build-system gnu-build-system)
(native-inputs
`(("unzip" ,unzip)))
(inputs
`(("readline" ,readline)))
(arguments
`(#:tests? #f ; 'check target does not exist.
#:phases
(modify-phases %standard-phases
(delete 'configure)
(replace 'install
(lambda* (#:key outputs #:allow-other-keys)
(let* ((out (assoc-ref outputs "out"))
(outbin (string-append out "/bin"))
(target (string-append outbin "/abc")))
(mkdir-p outbin)
(copy-file "abc" target)))))))
(home-page "http://people.eecs.berkeley.edu/~alanmi/abc/")
(synopsis "Sequential Logic Synthesis and Formal Verification")
(description "ABC is a program for sequential logic synthesis
and formal verification.")
;; FIXME use license: MIT Modern variant as described in:
;; <https://fedoraproject.org/wiki/Licensing:MIT>
(license license:expat))))
(define-public iverilog
(package
(name "iverilog")
(version "10.1.1")
(source (origin
(method url-fetch)
(uri
(string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/verilog-" version ".tar.gz"))
(sha256
(base32
"1nnassxvq30rnn0r2p85rkb2zwxk97p109y13x3vr365wzgpbapx"))))
(build-system gnu-build-system)
(native-inputs
`(("flex" ,flex)
("bison" ,bison)
("ghostscript" ,ghostscript) #| ps2pdf |#))
(home-page "http://iverilog.icarus.com/")
(synopsis "FPGA Verilog Simulation and Synthesis Tool")
(description "Icarus Verilog is a Verilog simulation and synthesis tool.
It operates as a compiler, compiling source code written in Verilog
(IEEE-1364) into some target format.
For batch simulation, the compiler can generate an intermediate form called
vvp assembly.
This intermediate form is executed by the ``vvp'' command.
For synthesis, the compiler generates netlists in the desired format.")
(license license:gpl2)))
(define-public yosys
(package
(name "yosys")
(version "0.6")
(source (origin
(method url-fetch)
(uri
(string-append "https://github.com/cliffordwolf/yosys/archive/"
name "-" version ".tar.gz"))
(sha256
(base32
"02j0c0m9dfyjccynalf0aggj6gy20k7iphpkg5cn6sdirlkv8gmx"))
(file-name (string-append name "-" version "-checkout.tar.gz"))
(modules '((guix build utils)))
(snippet
'(substitute* "Makefile"
(("ABCREV = .*") "ABCREV = default\n")))))
(build-system gnu-build-system)
(arguments
`(#:test-target "test"
#:make-flags (list "CC=gcc"
"CXX=g++"
(string-append "PREFIX=" %output))
#:phases
(modify-phases %standard-phases
(replace 'configure
(lambda* (#:key inputs (make-flags '()) #:allow-other-keys)
(zero? (apply system* "make" "config-gcc" make-flags))))
(add-after 'configure 'prepare-abc
(lambda* (#:key inputs #:allow-other-keys)
(let* ((sourceabc (assoc-ref inputs "abc"))
(sourcebin (string-append sourceabc "/bin"))
(source (string-append sourcebin "/abc")))
(mkdir-p "abc")
(call-with-output-file "abc/Makefile"
(lambda (port)
(format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
(copy-file source "abc/abc")
(zero? (system* "chmod" "+w" "abc/abc")))))
(add-before 'check 'fix-iverilog-references
(lambda* (#:key inputs native-inputs #:allow-other-keys)
(let* ((xinputs (or native-inputs inputs))
(xdirname (assoc-ref xinputs "iverilog"))
(iverilog (string-append xdirname "/bin/iverilog")))
(substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
"./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
"./techlibs/ice40/tests/test_bram.sh"
"./techlibs/ice40/tests/test_ffs.sh"
"./techlibs/xilinx/tests/bram1.sh"
"./techlibs/xilinx/tests/bram2.sh"
"./tests/bram/run-single.sh"
"./tests/realmath/run-test.sh"
"./tests/simple/run-test.sh"
"./tests/techmap/mem_simple_4x1_runtest.sh"
"./tests/tools/autotest.sh"
"./tests/vloghtb/common.sh")
(("if ! which iverilog") "if ! true")
(("iverilog ") (string-append iverilog " "))
(("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
iverilog
"\"")))))))))
;; TODO add xdot [patch the path to it here] as soon as I find out where it is.
(native-inputs
`(("pkg-config" ,pkg-config)
("python" ,python)
("bison" ,bison)
("flex" ,flex)
("gawk" , gawk) ; for the tests and "make" progress pretty-printing
("tcl" ,tcl) ; tclsh for the tests
("iverilog" ,iverilog) ; for the tests
))
(inputs
`(("tcl" ,tcl)
("readline" ,readline)
("libffi" ,libffi)
("abc" ,abc)))
(home-page "http://www.clifford.at/yosys/")
(synopsis "FPGA Verilog RTL Synthesizer")
(description "Yosys synthesizes Verilog-2005.")
(license license:isc)))
|