From mboxrd@z Thu Jan 1 00:00:00 1970 Path: news.gmane.org!not-for-mail From: ludovic.courtes@laas.fr (=?iso-8859-1?q?Ludovic_Court=E8s?=) Newsgroups: gmane.lisp.guile.user Subject: Fetch-and-store for PowerPC... and more! Date: Wed, 16 Mar 2005 09:48:08 +0100 Organization: LAAS-CNRS Message-ID: <87wts8rn7b.fsf@laas.fr> NNTP-Posting-Host: main.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: sea.gmane.org 1110964675 15166 80.91.229.2 (16 Mar 2005 09:17:55 GMT) X-Complaints-To: usenet@sea.gmane.org NNTP-Posting-Date: Wed, 16 Mar 2005 09:17:55 +0000 (UTC) Original-X-From: guile-user-bounces+guile-user=m.gmane.org@gnu.org Wed Mar 16 10:17:55 2005 Original-Received: from lists.gnu.org ([199.232.76.165]) by ciao.gmane.org with esmtp (Exim 4.43) id 1DBUey-0003h5-PV for guile-user@m.gmane.org; Wed, 16 Mar 2005 10:17:49 +0100 Original-Received: from localhost ([127.0.0.1] helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1DBUv0-0003Fp-2A for guile-user@m.gmane.org; Wed, 16 Mar 2005 04:34:23 -0500 Original-Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1DBUjh-0008Ks-Je for guile-user@gnu.org; Wed, 16 Mar 2005 04:22:41 -0500 Original-Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1DBUjN-0008Fg-Uc for guile-user@gnu.org; Wed, 16 Mar 2005 04:22:22 -0500 Original-Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1DBUj5-0007fJ-Br for guile-user@gnu.org; Wed, 16 Mar 2005 04:22:03 -0500 Original-Received: from [140.93.0.15] (helo=laas.laas.fr) by monty-python.gnu.org with esmtp (TLSv1:DES-CBC3-SHA:168) (Exim 4.34) id 1DBUBo-0000vt-9M for guile-user@gnu.org; Wed, 16 Mar 2005 03:47:41 -0500 Original-Received: by laas.laas.fr (8.13.1/8.13.1) with SMTP id j2G8lbAF027672; Wed, 16 Mar 2005 09:47:38 +0100 (CET) Original-To: guile-user@gnu.org X-URL: http://www.laas.fr/~lcourtes/ X-Revolutionary-Date: 26 =?iso-8859-1?q?Vent=F4se_an_213_de_la_R=E9volution?= X-PGP-Key-ID: 0xEB1F5364 X-PGP-Key: http://www.laas.fr/~lcourtes/ludovic.asc X-PGP-Fingerprint: 821D 815D 902A 7EAB 5CEE D120 7FBA 3D4F EB1F 5364 X-OS: powerpc-unknown-linux-gnu User-Agent: Gnus/5.1007 (Gnus v5.10.7) Emacs/21.3 (gnu/linux) X-Spam-Score: 0 () X-Scanned-By: MIMEDefang at CNRS-LAAS X-BeenThere: guile-user@gnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: General Guile related discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Original-Sender: guile-user-bounces+guile-user=m.gmane.org@gnu.org Errors-To: guile-user-bounces+guile-user=m.gmane.org@gnu.org X-MailScanner-To: guile-user@m.gmane.org Xref: news.gmane.org gmane.lisp.guile.user:4288 X-Report-Spam: http://spam.gmane.org/gmane.lisp.guile.user:4288 Hi, Guile 1.7.2 doesn't compile on PowerPC because the `FETCH_STORE' macro (in `arbiters.c') that is defined is the generic one. The generic version of `FETCH_STORE' relies on `scm_mutex_lock ()' and `scm_mutex_unlock ()' which are not (yet) implemented. So I implemented the PowerPC-version (32-bit) of `FETCH_STORE' (see below, this is a well-documented example). Below is also a tiny test program that shows that, well, it fetches and stores. ;-) After doing it, it occurred to me that maybe I should have look at Glibc before doing it. And it turns out that Glibc, indeed, already implements fetch-and-store for 15 architectures (see `always_swap ()' in `atomicity.h')... Unfortunately, this header doesn't seem to get installed, so we'll have to rip it (G++ also comes with its own implementation of fetch-and-store among other things anyway). Thanks, Ludovic. diff -ubB --show-c-function /home/ludo/tmp/guile-1.7.2/libguile/arbiters.c\~ /home/ludo/tmp/guile-1.7.2/libguile/arbiters.c --- /home/ludo/tmp/guile-1.7.2/libguile/arbiters.c~ 2004-08-22 03:49:10.000000000 +0200 +++ /home/ludo/tmp/guile-1.7.2/libguile/arbiters.c 2005-03-16 09:35:07.000000000 +0100 @@ -36,7 +36,9 @@ ENHANCE-ME: Add more cpu-specifics. glibc atomicity.h has some of the sort of thing required. FETCH_STORE could become some sort of - compare-and-store if that better suited what various cpus do. */ + compare-and-store if that better suited what various cpus do. Note: look + at the `always_swap ()' function is Glibc's `atomicity.h' in the `sysdeps' + directory. */ #if defined (__GNUC__) && defined (i386) && SIZEOF_SCM_T_BITS == 4 /* This is for i386 with the normal 32-bit scm_t_bits. The xchg instruction @@ -59,6 +61,28 @@ } while (0) #endif +#if defined (__GNUC__) && defined (__powerpc__) && SIZEOF_SCM_T_BITS == 4 + +/* On 32-bit PowerPC arches, we use the `lwarx' ("load word and reserve, + indexed") and `stwcx.' ("store word conditional, indexed") instructions. + In effect, data is loaded from MEM into FET and a reservation bit is set + to 1; `stwcx.' will only store STO into MEM if the reservation bit is + still set when it is executed, otherwise we start again the whole process. + This is a well-known example available in the "PowerPC Processor Reference + Guide" by Xilinx, for example. */ + +#define FETCH_STORE(fet,mem,sto) \ +do { \ + asm ("\n1:\n" \ + "\tlwarx %0,0,%1\n" \ + "\tstwcx. %2,0,%1\n" \ + "\tbne- 1b\n" \ + : "=&r" (fet) \ + : "r" (mem), "r" (sto)); \ +} while (0) + +#endif + #ifndef FETCH_STORE /* This is a generic version, with a mutex to ensure the operation is atomic. Unfortunately this approach probably makes arbiters no faster #include #include #define FETCH_STORE(fet,mem,sto) \ do { \ asm ("\n1:\n" \ "\tlwarx %0,0,%1\n" \ "\tstwcx. %2,0,%1\n" \ "\tbne- 1b\n" \ : "=&r" (fet) \ : "r" (mem), "r" (sto)); \ } while (0) static int in_memory = 12; int main (int argc, char *argv[]) { int old_value = 0, new_value = 7; while (1) { int actual_old_value = in_memory; FETCH_STORE (old_value, &in_memory, new_value); printf ("old=%i, new=%i, mem=%i\n", old_value, new_value, in_memory); assert (old_value == actual_old_value); assert (new_value == in_memory); new_value += old_value; } return 0; } _______________________________________________ Guile-user mailing list Guile-user@gnu.org http://lists.gnu.org/mailman/listinfo/guile-user