Re: OT: x86 assembly timings/size

[Marius Vollmer <mvo@zagadka.de>]

Allister MacLeod <amacleod@mv3d.com> writes:

> I forget the original expansion of lea.. maybe load extended
> address?

My guess would be "load effective address"... but it's not _really_
relevant, right? :-)

> I really ought to go look at an assembly reference myself.  A brief
> google for "x86 assembly timings lea" didn't turn up anything
> immediately and eminently useful in the first few hits.

I doubt that there are any simple and reliable timing diagrams for
IA-32 instructions in general.  I would imagine tho that lea uses the
addressing unit while shl goes thru the regular integer unit, on chips
that make the distinction.  It's all pretty idle speculation on my
part, tho.  Assembler used to be fun on the 68k but I've never written
more than three consecutive lines of x86 assembler.

> Anyway, probably the one with just lea's is slightly faster.
> Certainly unless the D=R1+R2*N instruction is more than twice as big
> as D=D+R1 or D=D<<N, the resulting binary will be smaller :^)

The main point is that it doesn't pay to try to outsmart the compiler.
Isn't that a comfortable insight?  I wouldn't want to worry whether
n-- > 0 is faster than --n >= 0.  Especially when n is unsigned...

-- 
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