From mboxrd@z Thu Jan 1 00:00:00 1970 Path: news.gmane.org!.POSTED.blaine.gmane.org!not-for-mail From: Bruno Haible Newsgroups: gmane.lisp.guile.devel Subject: support for mips32r6 Date: Fri, 30 Aug 2019 10:09:47 +0200 Message-ID: <92188107.04DtdhtvNo@omega> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="nextPart11785763.mux1EYeVpU" Content-Transfer-Encoding: 7Bit Injection-Info: blaine.gmane.org; posting-host="blaine.gmane.org:195.159.176.226"; logging-data="123500"; mail-complaints-to="usenet@blaine.gmane.org" User-Agent: KMail/5.1.3 (Linux/4.4.0-159-generic; KDE/5.18.0; x86_64; ; ) To: guile-devel@gnu.org Original-X-From: guile-devel-bounces+guile-devel=m.gmane.org@gnu.org Fri Aug 30 10:10:38 2019 Return-path: Envelope-to: guile-devel@m.gmane.org Original-Received: from lists.gnu.org ([209.51.188.17]) by blaine.gmane.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1i3bzO-000Vsu-Rn for guile-devel@m.gmane.org; Fri, 30 Aug 2019 10:10:36 +0200 Original-Received: from localhost ([::1]:57000 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3bzM-000582-Gx for guile-devel@m.gmane.org; Fri, 30 Aug 2019 04:10:32 -0400 Original-Received: from eggs.gnu.org ([2001:470:142:3::10]:36285) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i3byp-00055t-6W for guile-devel@gnu.org; Fri, 30 Aug 2019 04:10:01 -0400 Original-Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i3byk-0004G8-E7 for guile-devel@gnu.org; Fri, 30 Aug 2019 04:09:56 -0400 Original-Received: from mo6-p00-ob.smtp.rzone.de ([2a01:238:20a:202:5300::2]:12509) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i3byi-0003u1-Id for guile-devel@gnu.org; Fri, 30 Aug 2019 04:09:54 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1567152588; s=strato-dkim-0002; d=clisp.org; h=Message-ID:Date:Subject:To:From:X-RZG-CLASS-ID:X-RZG-AUTH:From: Subject:Sender; bh=CyCnCq+JbBvlkuzA0130y8yzP+BAKsMU9rNV1NaUHHs=; b=IuZiABRcfsIbDpJXNfW8PpdvP6g6hSmdUPSkQAp5GwpbWaRheG2A3ESeSP6TFHsw/S 52Bz81+VGbItgBLNr5qBlhgAFuO3AkV9dG3eJUERtUayWvPqXWkEWMpBjxeg+vrdHB3i 0sc5GGYFtOooqjQUY8bIVy2AUnSwsGE476cASzmG+NcaruzzrRB11R2AMs891F8AdXbo ZmvpmhKaueEU4HzO+vpSW1KXxwtmzcwLIobxAzU0Qbka8bapZEEXTl3zIKk7mXgdx7EI /bvnrg6AFq4LMI8ZOjC0MKgOPO8PzvbI96a1fQ6VCrjdmqYL29gV1DeZM8vXz1lhthwW AaZw== X-RZG-AUTH: ":Ln4Re0+Ic/6oZXR1YgKryK8brlshOcZlIWs+iCP5vnk6shH+AHjwLuWOGaf0zJZW" X-RZG-CLASS-ID: mo00 Original-Received: from bruno.haible.de by smtp.strato.de (RZmta 44.27.0 DYNA|AUTH) with ESMTPSA id U0b0dfv7U89mJpM (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Fri, 30 Aug 2019 10:09:48 +0200 (CEST) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a01:238:20a:202:5300::2 X-BeenThere: guile-devel@gnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "Developers list for Guile, the GNU extensibility library" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: guile-devel-bounces+guile-devel=m.gmane.org@gnu.org Original-Sender: "guile-devel" Xref: news.gmane.org gmane.lisp.guile.devel:20056 Archived-At: This is a multi-part message in MIME format. --nextPart11785763.mux1EYeVpU Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Hi, A libffcall bug report [1] made me aware of an incompatible change in the MIPS ISAs. Namely, for jumping to an address given in a register, starting with mips32r6, the existing 'jr' instruction does not work any more: it produces an 'illegal instruction'. There are many documents of the MIPS ISAs, and before 2014 they described two instructions JR and JALR: JR jumps to the address in register JALR , jumps to the address in register and puts the old PC + 8 into register In particular, JR [SPECIAL, rs, 00000, 00000, hint, 001000] is equivalent to JALR $0, [SPECIAL, rs, 00000, 00000, hint, 001001] (because writing to $0 is a no-op). In the documents that consider the MIPS32 R6 architecture, such as [2] from 2014 - look at the descriptions of JR and JALR - you see that - in order to get the effect of JR, the bit pattern of JALR with destination $0 has to be used, - in the JALR instruction, the destination $0 is no longer allowed; this is merely a hint for the disassembler. You can see that the GNU assembler has been adjusted. First, see the different bit patterns: $ cat foo.s .text j $25 nop jal $0,$25 nop # Assemble this using binutils 2.16.1: $ mips64-linux-as -32 -o foo.o foo.s $ mips64-linux-objdump --disassemble foo.o foo.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 03200008 jr t9 4: 00000000 nop 8: 03200009 jalr zero,t9 c: 00000000 nop ... # Now, see how a newer GNU assembler (binutils 2.27) and option -mips32r6 # produce a different result: $ mips64-linux-as -32 -mips32r6 -o foo.o foo.s $ mips64-linux-objdump --disassemble foo.o [binutils 2.16.1] foo.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 03200009 jalr zero,t9 4: 00000000 nop 8: 03200009 jalr zero,t9 c: 00000000 nop ... $ mips64-linux-objdump --disassemble foo.o [binutils 2.27] foo.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 03200009 jr t9 4: 00000000 nop 8: 03200009 jr t9 c: 00000000 nop ... Note that the JALR $0, instruction can be used on all architectures; I verified this by looking at old MIPS ISA documentations from 1995, and by looking at the source code of QEMU. Find attached a fix for GNU guile, that mirrors the one I submitted for GNU lightning [3] (untested). Bruno [1] https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=925129 [2] http://hades.mech.northwestern.edu/images/1/16/MIPS32_Architecture_Volume_II-A_Instruction_Set.pdf [3] https://lists.gnu.org/archive/html/lightning/2019-08/msg00010.html --nextPart11785763.mux1EYeVpU Content-Disposition: attachment; filename="mips32r6-fix.diff" Content-Transfer-Encoding: 7Bit Content-Type: text/x-patch; charset="UTF-8"; name="mips32r6-fix.diff" diff --git a/libguile/lightening/lightening/mips-cpu.c b/libguile/lightening/lightening/mips-cpu.c index 7ab58b8..704a2cd 100644 --- a/libguile/lightening/lightening/mips-cpu.c +++ b/libguile/lightening/lightening/mips-cpu.c @@ -379,7 +379,11 @@ static void _nop(jit_state_t*,int32_t); # define BGTZ(rs,im) hrri(MIPS_BGTZ,rs,_ZERO_REGNO,im) # define BNE(rs,rt,im) hrri(MIPS_BNE,rs,rt,im) # define JALR(r0) hrrrit(MIPS_SPECIAL,r0,0,_RA_REGNO,0,MIPS_JALR) -# define JR(r0) hrrrit(MIPS_SPECIAL,r0,0,0,0,MIPS_JR) +# if 1 /* supports MIPS32 R6 */ +# define JR(r0) hrrrit(MIPS_SPECIAL,r0,0,0,0,MIPS_JALR) +# else /* does not support MIPS32 R6 */ +# define JR(r0) hrrrit(MIPS_SPECIAL,r0,0,0,0,MIPS_JR) +# endif # define J(i0) hi(MIPS_J,i0) # define MOVZ(rd,rs,rt) hrrrit(0,rs,rt,rd,0,MIPS_MOVZ) # define comr(r0,r1) xori(r0,r1,-1) --nextPart11785763.mux1EYeVpU--