From: Mark H Weaver <mhw@netris.org>
To: Noah Lavine <noah.b.lavine@gmail.com>
Cc: "Andy Wingo" <wingo@pobox.com>, "Ludovic Courtès" <ludo@gnu.org>,
guile-devel@gnu.org
Subject: Re: Register VM WIP
Date: Wed, 16 May 2012 00:23:36 -0400 [thread overview]
Message-ID: <871umkbvp3.fsf@netris.org> (raw)
In-Reply-To: <CA+U71=Psa=j5goZDCXE0cORu8Ly7ApbQH94XCkjNMM3aTrZA0A@mail.gmail.com> (Noah Lavine's message of "Tue, 15 May 2012 20:39:02 -0400")
Noah Lavine <noah.b.lavine@gmail.com> writes:
>>> The register based VMs I've seen ignore this issue by allowing for an
>>> infinite set of registers. :)
>>
>> Indeed, that's the plan :) The first shot at an allocator will look a
>> lot like the one in (language tree-il analyze).
>
> That was a bit surprising to me. Do you mean that the register pool
> will grow and shrink for each function call? Is that why the stack
> frames can be fixed-size?
It's surprising to me for another reason: in order to make the
instructions reasonably compact, only a limited number of bits are
available in each instruction to specify which registers to use.
Mark
next prev parent reply other threads:[~2012-05-16 4:23 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-11 16:19 Register VM WIP Andy Wingo
2012-05-11 20:29 ` Stefan Israelsson Tampe
2012-05-16 15:01 ` Andy Wingo
2012-05-14 21:09 ` Ludovic Courtès
2012-05-14 21:28 ` Andrew Gwozdziewycz
2012-05-15 18:45 ` Andy Wingo
2012-05-16 0:39 ` Noah Lavine
2012-05-16 4:23 ` Mark H Weaver [this message]
2012-05-16 7:15 ` Andy Wingo
2012-05-16 13:44 ` Mark H Weaver
2012-05-16 14:00 ` David Kastrup
2012-05-16 14:54 ` Noah Lavine
2012-05-16 15:05 ` Andy Wingo
2012-05-16 20:39 ` Ludovic Courtès
2012-05-16 14:58 ` Andy Wingo
2012-05-16 16:27 ` Mark H Weaver
2012-05-16 16:39 ` Andy Wingo
2012-05-16 18:23 ` Noah Lavine
2012-05-16 7:10 ` Andy Wingo
2012-05-15 18:49 ` Andy Wingo
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