I'm attempting to use buildroot to cross compile guile 3.0.2 for 32bit arm (rpi3).
Note that guile runs fine with the jit disabled by GUILE_JIT_THRESHOLD=-1
When guile starts, I get an "Illegal instruction".
# GUILE_JIT_LOG=3 guile
jit: allocated code arena, 0x74f43000-0x74f83000
jit: mcode: 0x74f43000,+44
jit: mcode: 0x74f43030,+56
jit: mcode: 0x74f43070,+8
jit: vcode: start=0xa2261c,+6 entry=+0
jit: Instruction first seen at vcode 0xa2261c: instrument-entry
jit: Instruction at vcode 0xa2261c: instrument-entry
jit: Instruction first seen at vcode 0xa22624: assert-nargs-ee
jit: Instruction at vcode 0xa22624: assert-nargs-ee
jit: Instruction first seen at vcode 0xa22628: subr-call
jit: Instruction at vcode 0xa22628: subr-call
jit: Instruction first seen at vcode 0xa2262c: handle-interrupts
jit: Instruction at vcode 0xa2262c: handle-interrupts
jit: Instruction first seen at vcode 0xa22630: return-values
jit: Instruction at vcode 0xa22630: return-values
jit: mcode: 0x74f43080,+200
jit: created /tmp/perf-287.map
jit: entering mcode: 0x74f43080
Illegal instruction
I got cross-gdb working. Here is another run, with the disassembled code
jit: mcode: 0x74edb080,+200
jit: created /tmp/perf-252.map
jit: entering mcode: 0x74edb080
Dump of assembler code from 0x74edb080 to 0x74edb148:
0x74edb080: 0d 1a subs r5, r1, r0
0x74edb082: 20 2d cmp r5, #32
0x74edb084: 40 f0 35 80 bne.w 0x74edb0f2
0x74edb088: 4e f2 28 65 movw r5, #58920 ; 0xe628
0x74edb08c: c0 f2 cb 05 movt r5, #203 ; 0xcb
0x74edb090: 65 60 str r5, [r4, #4]
0x74edb092: d0 f8 10 c0 ldr.w r12, [r0, #16]
0x74edb096: 81 68 ldr r1, [r0, #8]
0x74edb098: 02 68 ldr r2, [r0, #0]
0x74edb09a: 60 46 mov r0, r12
0x74edb09c: 00 f0 48 e8 blx 0x74edb130 ; <- lr reg indicates failing code called from here.
0x74edb0a0: 06 46 mov r6, r0
0x74edb0a2: 16 f0 06 0f tst.w r6, #6
0x74edb0a6: 40 f0 07 80 bne.w 0x74edb0b8
0x74edb0aa: 56 f8 00 5e ldrt r5, [r6]
0x74edb0ae: 05 f0 7f 05 and.w r5, r5, #127 ; 0x7f
0x74edb0b2: 3f 2d cmp r5, #63 ; 0x3f
0x74edb0b4: 00 f0 25 80 beq.w 0x74edb102
0x74edb0b8: e1 68 ldr r1, [r4, #12]
0x74edb0ba: a1 f1 08 00 sub.w r0, r1, #8
0x74edb0be: a0 60 str r0, [r4, #8]
0x74edb0c0: 40 f8 00 6e strt r6, [r0]
0x74edb0c4: 04 f1 48 05 add.w r5, r4, #72 ; 0x48
0x74edb0c8: bf f3 5b 8f dmb ish
0x74edb0cc: 55 f8 00 5e ldrt r5, [r5]
0x74edb0d0: bf f3 5b 8f dmb ish
0x74edb0d4: 40 f2 04 3c movw r12, #772 ; 0x304
0x74edb0d8: b5 eb 0c 0f cmp.w r5, r12
0x74edb0dc: 40 f0 19 80 bne.w 0x74edb112
0x74edb0e0: e5 68 ldr r5, [r4, #12]
0x74edb0e2: 29 69 ldr r1, [r5, #16]
0x74edb0e4: c9 00 lsls r1, r1, #3
0x74edb0e6: 69 18 adds r1, r5, r1
0x74edb0e8: e1 60 str r1, [r4, #12]
0x74edb0ea: 55 f8 00 ee ldrt lr, [r5]
0x74edb0ee: 70 47 bx lr
0x74edb0f0: 00 be bkpt 0x0000
0x74edb0f2: 4e f2 24 65 movw r5, #58916 ; 0xe624
0x74edb0f6: c0 f2 cb 05 movt r5, #203 ; 0xcb
0x74edb0fa: 65 60 str r5, [r4, #4]
0x74edb0fc: 20 46 mov r0, r4
0x74edb0fe: 00 f0 1b e8 ; <UNDEFINED> instruction: 0xf000e81b
0x74edb102: 20 46 mov r0, r4
0x74edb104: 31 46 mov r1, r6
0x74edb106: 00 f0 1b e8 ; <UNDEFINED> instruction: 0xf000e81b
0x74edb10a: a0 68 ldr r0, [r4, #8]
0x74edb10c: e1 68 ldr r1, [r4, #12]
0x74edb10e: ff f7 d9 bf b.w 0x74edb0c4
0x74edb112: e5 6c ldr r5, [r4, #76] ; 0x4c
0x74edb114: 00 2d cmp r5, #0
0x74edb116: 7f f4 e3 af bne.w 0x74edb0e0
0x74edb11a: 4e f2 2c 65 movw r5, #58924 ; 0xe62c
0x74edb11e: c0 f2 cb 05 movt r5, #203 ; 0xcb
0x74edb122: 65 60 str r5, [r4, #4]
0x74edb124: ff f7 84 ff bl 0x74edb030
0x74edb128: e1 68 ldr r1, [r4, #12]
0x74edb12a: ff f7 cb bf b.w 0x74edb0c4
0x74edb12e: 00 be bkpt 0x0000
;; Here is the pc at Illegal instruction time.
=> 0x74edb130: 00 4f ldr r7, [pc, #0] ; (0x74edb134)
0x74edb132: bf 46 mov pc, r7 ; pc <- 0x76e9_8d18
0x74edb134: 18 8d e9 76 ; data 0x76e9_8d18
0x74edb138: 00 4f ldr r7, [pc, #0] ; (0x74edb13c)
0x74edb13a: bf 46 mov pc, r7 ; pc <- 0x76e8_8e48
0x74edb13c: 48 8e e8 76 ; data 0x76e8_8e48
0x74edb140: 00 4f ldr r7, [pc, #0] ; (0x74edb144)
0x74edb142: bf 46 mov pc, r7 ; pc <- 0x76e_e3758
0x74edb144: 58 37 ee 76 ; data 0x76ee_3758
(gdb) info registers
r0 0x75106880 1964009600
r1 0x750f2930 1963927856
r2 0x74f7b7a8 1962391464
r3 0x74edb001 1961734145
r4 0x76931e00 1989352960
r5 0xcbe628 13362728
r6 0x76931e00 1989352960
r7 0x74edb080 1961734272
r8 0x76f61ec0 1995841216
r9 0xcbe61c 13362716
r10 0x4 4
r11 0x76f2c000 1995620352
r12 0x75106880 1964009600
sp 0x7ef65578 0x7ef65578
lr 0x74edb0a1 1961734305
pc 0x74edb130 0x74edb130
cpsr 0x60000010 1610612752
fpscr 0x0 0
Now, I'm not very familiar with arm and arm-thumb, but that code *seems* to be right to me.
Looks like it was generated by emit_veneer() in libguile/lightening/lightening/arm-cpu.c
So what could be wrong here? How could this code generate an illegal instruction error?
Where do I go from here?
Thanks,
-Dale