Re: Lisp_Marker size on 32bit systems

[Paul Eggert <eggert@cs.ucla.edu>]

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Stefan Monnier wrote:

> I still wonder why it would be slower at all.

My guess is cache effects. My processor has a cache line size of 64 bytes, so if 
objects are allocated in 32-byte chunks they won't straddle cache boundaries and 
code will be less likely to thrash the cache. I ran this benchmark in the 'lisp' 
subdirectory:

EMACSLOADPATH= perf stat -dd '../src/emacs' -batch --no-site-file --no-site-lisp 
--eval '(setq load-prefer-newer t)'  -f batch-byte-compile org/org.el

and am attaching the results for the 24-bit allocation (a bit slower) and the 
32-bit allocation (a bit faster), and they are in line with this guess.

>> Maybe we should be using 4 mark bits instead of 3?
> On 32bit systems, both cons cells and float cells use 8 bytes each, so
> aligning on multiples of 16 would double their memory use.

We'd use two tags for both conses and float cells, so that shouldn't be a problem.

> it's not clear
> what the extra tags would be useful for.

Presumably to help performance elsewhere. Admittedly I'm blue-skying a bit here.

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 Performance counter stats for '../src/emacs -batch --no-site-file --no-site-lisp --eval (setq load-prefer-newer t) -f batch-byte-compile org/org.el':

       3710.809824      task-clock:u (msec)       #    0.998 CPUs utilized          
                 0      context-switches:u        #    0.000 K/sec                  
                 0      cpu-migrations:u          #    0.000 K/sec                  
             4,298      page-faults:u             #    0.001 M/sec                  
     9,414,411,487      cycles:u                  #    2.537 GHz                      (18.79%)
       757,273,968      stalled-cycles-frontend:u #    8.04% frontend cycles idle     (18.80%)
     4,395,722,568      stalled-cycles-backend:u  #   46.69% backend cycles idle      (18.80%)
     9,301,424,026      instructions:u            #    0.99  insn per cycle         
                                                  #    0.47  stalled cycles per insn  (18.79%)
     1,390,988,726      branches:u                #  374.848 M/sec                    (18.76%)
        67,045,930      branch-misses:u           #    4.82% of all branches          (18.74%)
     5,219,768,450      L1-dcache-loads:u         # 1406.639 M/sec                    (18.73%)
        43,583,947      L1-dcache-load-misses:u   #    0.83% of all L1-dcache hits    (18.72%)
        85,736,523      LLC-loads:u               #   23.105 M/sec                    (18.73%)
        14,635,030      LLC-load-misses:u         #   17.07% of all LL-cache hits     (18.73%)
     2,429,036,804      L1-icache-loads:u         #  654.584 M/sec                    (18.73%)
         7,260,772      L1-icache-load-misses:u   #    0.30% of all L1-icache hits    (18.72%)
     5,206,401,315      dTLB-loads:u              # 1403.036 M/sec                    (18.72%)
         4,878,637      dTLB-load-misses:u        #    0.09% of all dTLB cache hits   (18.72%)
     2,418,273,074      iTLB-loads:u              #  651.683 M/sec                    (18.75%)
             2,946      iTLB-load-misses:u        #    0.00% of all iTLB cache hits   (18.77%)

       3.718081199 seconds time elapsed


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 Performance counter stats for '../src/emacs -batch --no-site-file --no-site-lisp --eval (setq load-prefer-newer t) -f batch-byte-compile org/org.el':

       3643.107970      task-clock:u (msec)       #    0.998 CPUs utilized          
                 0      context-switches:u        #    0.000 K/sec                  
                 0      cpu-migrations:u          #    0.000 K/sec                  
             4,320      page-faults:u             #    0.001 M/sec                  
     9,235,689,147      cycles:u                  #    2.535 GHz                      (18.77%)
       683,279,700      stalled-cycles-frontend:u #    7.40% frontend cycles idle     (18.74%)
     4,395,369,277      stalled-cycles-backend:u  #   47.59% backend cycles idle      (18.73%)
     9,226,971,053      instructions:u            #    1.00  insn per cycle         
                                                  #    0.48  stalled cycles per insn  (18.74%)
     1,360,574,869      branches:u                #  373.465 M/sec                    (18.75%)
        68,352,263      branch-misses:u           #    5.02% of all branches          (18.75%)
     5,125,592,214      L1-dcache-loads:u         # 1406.928 M/sec                    (18.74%)
        41,529,042      L1-dcache-load-misses:u   #    0.81% of all L1-dcache hits    (18.74%)
        77,752,725      LLC-loads:u               #   21.342 M/sec                    (18.74%)
        14,778,615      LLC-load-misses:u         #   19.01% of all LL-cache hits     (18.75%)
     2,394,079,664      L1-icache-loads:u         #  657.153 M/sec                    (18.74%)
         6,663,498      L1-icache-load-misses:u   #    0.28% of all L1-icache hits    (18.74%)
     5,164,701,717      dTLB-loads:u              # 1417.664 M/sec                    (18.74%)
         4,443,995      dTLB-load-misses:u        #    0.09% of all dTLB cache hits   (18.76%)
     2,345,758,968      iTLB-loads:u              #  643.889 M/sec                    (18.78%)
             3,369      iTLB-load-misses:u        #    0.00% of all iTLB cache hits   (18.79%)

       3.650332037 seconds time elapsed