bug#22368: Another way to produce the same result

[John Chapple <jrchapple@sympatico.ca>]

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Hello again, Ladies and/or Gentlemen,

I have found another method to reproduce this problem that perhaps is clearer:

Open the attached file.

Using the mouse, select Edit | Select All .

Using the mouse, select VHDL | Comment | (Un)Comment Out Region.

Line 14 will now be rejected by any VHDL compiler.  The file is saved to disk as it appears on the screen.  I checked with another editor.

Cheers
John
 		 	   		  

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--library	ieee;
--use		ieee.std_logic_1164.all;

--library work;
--use		work.definitions.all;

--entity ccf_operation is
--port(
--	flags_in:	in	std_logic_vector(7 downto 0);
--	flags_out:	out	std_logic_vector(7 downto 0)
--);
--end;

---- Tested with Modelsim 2015/11/25, works.

--architecture struct_ccf_operation of ccf_operation is
--begin
--	-- A point of disagreement has been found between the Z80 user manual
--	-- and Lance Levinthal's book entitled "Z80 Assembly Language Programming".
--	-- The Z80 user manual says the half-carry bit gets the previous carry;
--	-- Levinthal says the half-carry bit is unchanged.  For now, go with
--	-- Levinthal's version as the Z80 users manual is inconsistent with
--	-- itself on other instructions.  At this time, no such inconsistencies
--	-- have been found with Levinthal's work.

--	flags_out <= (	carry_bit => not flags_in(carry_bit),
----					half_carry_bit <= flags_in(carry_bit),
--					others => '0');
--end;

--library	ieee;
--use		ieee.std_logic_1164.all;

--library work;
--use		work.definitions.all;