* How to disable "_i" insertion on signals in emacs VHDL mode
@ 2007-01-31 19:58 chris.plachta
2007-01-31 21:13 ` Nicolas Matringe
2007-02-01 3:13 ` Mike Treseler
0 siblings, 2 replies; 3+ messages in thread
From: chris.plachta @ 2007-01-31 19:58 UTC (permalink / raw)
To: help-gnu-emacs
Hi,
Does anyone know how to disable the automatic insertion of "_i" on
signals that are connect to a instance port map?
For example, when I use the vhdl-paste-port-instance command on a
model with the ports called "rst_l" and "clk", it gives me this:
instance: clk_model
port map (
rst_l => rst_l_i,
clk => clk_i);
I want to get rid of the "_i" convention and use identical names for
the port and the signal.
Thanks in advance...
Chris
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: How to disable "_i" insertion on signals in emacs VHDL mode
2007-01-31 19:58 How to disable "_i" insertion on signals in emacs VHDL mode chris.plachta
@ 2007-01-31 21:13 ` Nicolas Matringe
2007-02-01 3:13 ` Mike Treseler
1 sibling, 0 replies; 3+ messages in thread
From: Nicolas Matringe @ 2007-01-31 21:13 UTC (permalink / raw)
To: help-gnu-emacs
chris.plachta@gmail.com a écrit :
> Hi,
>
> Does anyone know how to disable the automatic insertion of "_i" on
> signals that are connect to a instance port map?
>
> For example, when I use the vhdl-paste-port-instance command on a
> model with the ports called "rst_l" and "clk", it gives me this:
>
>
> instance: clk_model
> port map (
> rst_l => rst_l_i,
> clk => clk_i);
>
> I want to get rid of the "_i" convention and use identical names for
> the port and the signal.
Hi
I still don't know the actual variable name ...
See VHDL>Options>Port>Actual Port Names...
Nicolas
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: How to disable "_i" insertion on signals in emacs VHDL mode
2007-01-31 19:58 How to disable "_i" insertion on signals in emacs VHDL mode chris.plachta
2007-01-31 21:13 ` Nicolas Matringe
@ 2007-02-01 3:13 ` Mike Treseler
1 sibling, 0 replies; 3+ messages in thread
From: Mike Treseler @ 2007-02-01 3:13 UTC (permalink / raw)
To: help-gnu-emacs
chris.plachta@gmail.com wrote:
> Does anyone know how to disable the automatic insertion of "_i" on
> signals that are connect to a instance port map?
>
If I say:
customize-apropos port
I see my settings:
Vhdl Actual Port Name: Hide
>From regexp: .*
To string : \&_s
State: this option has been set and saved.
Specifies how actual port names are obtained from formal port names. Hide
In a component instantiation, an actual port name can be obtained by
modifying the formal port name (e.g. attaching or stripping off a
substring).
FROM REGEXP is a regular expression matching the original name:
".*" matches the entire string
"\(...\)" matches a substring
TO STRING specifies the string to be inserted as new name:
"\&" means substitute entire matched text
"\N" means substitute what matched the Nth "\(...\)"
Examples:
".*" "\&" inserts original string
".*" "\&_i" attaches "_i" to original string
"\(.*\)_[io]$" "\1" strips off "_i" or "_o" from original string
".*" "foo" inserts constant string "foo"
".*" "" inserts empty string
^ permalink raw reply [flat|nested] 3+ messages in thread
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2007-01-31 19:58 How to disable "_i" insertion on signals in emacs VHDL mode chris.plachta
2007-01-31 21:13 ` Nicolas Matringe
2007-02-01 3:13 ` Mike Treseler
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