Re: How to disable "_i" insertion on signals in emacs VHDL mode

[Mike Treseler <mike_treseler@comcast.net>]

chris.plachta@gmail.com wrote:

> Does anyone know how to disable the automatic insertion of "_i" on
> signals that are connect to a instance port map?
> 


If I say:
customize-apropos port

I see my settings:

Vhdl Actual Port Name: Hide
>From regexp: .*
To string  : \&_s
   State: this option has been set and saved.
Specifies how actual port names are obtained from formal port names. Hide
In a component instantiation, an actual port name can be obtained by
modifying the formal port name (e.g. attaching or stripping off a
substring).

FROM REGEXP is a regular expression matching the original name:
  ".*"       matches the entire string
  "\(...\)"  matches a substring
TO STRING specifies the string to be inserted as new name:
  "\&"  means substitute entire matched text
  "\N"  means substitute what matched the Nth "\(...\)"
Examples:
  ".*"           "\&"    inserts original string
  ".*"           "\&_i"  attaches "_i" to original string
  "\(.*\)_[io]$" "\1"    strips off "_i" or "_o" from original string
  ".*"           "foo"   inserts constant string "foo"
  ".*"           ""      inserts empty string