bug#5136: Request to update vhdl-mode and verilog-mode

bug#5136: Request to update vhdl-mode and verilog-mode

[Chitlesh GOORAH]

Hello there,

The following modes bundled in emacs-23.1-13.fc12.i686 are very old
compared to the lastest upstream releases.

vhdl-mode
http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html

verilog-mode
http://www.verilog.com/verilog-mode.html

I would like to request these to be updated within emacs sources so
that linux distributions don't have to package them separately. This
request is related to the work done behind Fedora Electronic Lab to
give people a complete FOSS platform for micro-nanoelectronic design
engineering, thus making emacs one of the core tools for mixed-signal
hardware design, coupled with other emacs mode not included in the
emacs sources.

Kind regards,
Chitlesh Goorah
http://spins.fedoraproject.org/fel/

bug#5136: Request to update vhdl-mode and verilog-mode

[Dan Nicolaescu]

Chitlesh GOORAH <chitlesh.goorah@gmail.com> writes:

  > Hello there,
  > 
  > The following modes bundled in emacs-23.1-13.fc12.i686 are very old
  > compared to the lastest upstream releases.
  > 
  > vhdl-mode
  > http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html

Reto can you please send a patch + ChangeLog for the changes?

  > verilog-mode
  > http://www.verilog.com/verilog-mode.html

I've asked the authors for updates, they will be installed as soon as we
get them.

  > I would like to request these to be updated within emacs sources so
  > that linux distributions don't have to package them separately. This
  > request is related to the work done behind Fedora Electronic Lab to
  > give people a complete FOSS platform for micro-nanoelectronic design
  > engineering, thus making emacs one of the core tools for mixed-signal
  > hardware design, coupled with other emacs mode not included in the
  > emacs sources.

Why isn't that mode included?  What mode is it?

bug#5136: Request to update vhdl-mode and verilog-mode

[Chitlesh GOORAH]

On Mon, Dec 7, 2009 at 8:56 AM, Dan Nicolaescu <> wrote:
> Chitlesh GOORAH <> writes:
>
>  > Hello there,
>  >
>  > The following modes bundled in emacs-23.1-13.fc12.i686 are very old
>  > compared to the lastest upstream releases.
>  >
>  > vhdl-mode
>  > http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html
>
> Reto can you please send a patch + ChangeLog for the changes?
>
>  > verilog-mode
>  > http://www.verilog.com/verilog-mode.html
>
> I've asked the authors for updates, they will be installed as soon as we
> get them.
>
>  > I would like to request these to be updated within emacs sources so
>  > that linux distributions don't have to package them separately. This
>  > request is related to the work done behind Fedora Electronic Lab to
>  > give people a complete FOSS platform for micro-nanoelectronic design
>  > engineering, thus making emacs one of the core tools for mixed-signal
>  > hardware design, coupled with other emacs mode not included in the
>  > emacs sources.
>
> Why isn't that mode included?  What mode is it?
>

Hello,

I don't know why, but these are my views:

irsim-mode (not included) has two features - highlight and
indentation. Simple and can be integrated within emacs sources.

spice-mode is very old however was designed to use with proprietary
simulators. We are currently testing and ensuring that opensource
spice simulators and viewers can be used with this mode. If you are
interested in putting it into emacs sources, please take our patches
that we are currently preparing.
https://bugzilla.redhat.com/show_bug.cgi?id=544745
Let me know whether you are interested in adding it to the emacs
sources so that after fixing spice-mode, we'll close the package
review and won't push it to our repositories.

Similarly, for vhdl-mode (included within emacs sources), weirdly does
not support ghdl or freehdl out of the box, but only proprietary
simulators. Can your vhdl-mode maintainer for emacs can fix it and put
ghdl as default simulator please ?

Kind regards,
Chitlesh

bug#5136: Request to update vhdl-mode and verilog-mode

[Dan Nicolaescu]

Chitlesh GOORAH <chitlesh.goorah@gmail.com> writes:

  > On Mon, Dec 7, 2009 at 8:56 AM, Dan Nicolaescu <> wrote:
  > > Chitlesh GOORAH <> writes:
  > >
  > >  > Hello there,
  > >  >
  > >  > The following modes bundled in emacs-23.1-13.fc12.i686 are very old
  > >  > compared to the lastest upstream releases.
  > >  >
  > >  > vhdl-mode
  > >  > http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html
  > >
  > > Reto can you please send a patch + ChangeLog for the changes?
  > >
  > >  > verilog-mode
  > >  > http://www.verilog.com/verilog-mode.html
  > >
  > > I've asked the authors for updates, they will be installed as soon as we
  > > get them.
  > >
  > >  > I would like to request these to be updated within emacs sources so
  > >  > that linux distributions don't have to package them separately. This
  > >  > request is related to the work done behind Fedora Electronic Lab to
  > >  > give people a complete FOSS platform for micro-nanoelectronic design
  > >  > engineering, thus making emacs one of the core tools for mixed-signal
  > >  > hardware design, coupled with other emacs mode not included in the
  > >  > emacs sources.
  > >
  > > Why isn't that mode included?  What mode is it?
  > >
  > 
  > Hello,
  > 
  > I don't know why, but these are my views:

Packages are added to emacs when someone takes interest in them and
takes them through the process.
The most important is asking the authors to sign a copyright assignment
to the FSF for the package in question.

  > irsim-mode (not included) has two features - highlight and
  > indentation. Simple and can be integrated within emacs sources.

  > spice-mode is very old however was designed to use with proprietary
  > simulators. We are currently testing and ensuring that opensource
  > spice simulators and viewers can be used with this mode. If you are
  > interested in putting it into emacs sources, please take our patches
  > that we are currently preparing.
  > https://bugzilla.redhat.com/show_bug.cgi?id=544745
  > Let me know whether you are interested in adding it to the emacs
  > sources so that after fixing spice-mode, we'll close the package
  > review and won't push it to our repositories.

  > Similarly, for vhdl-mode (included within emacs sources), weirdly does
  > not support ghdl or freehdl out of the box, but only proprietary
  > simulators. Can your vhdl-mode maintainer for emacs can fix it and put
  > ghdl as default simulator please ?

There's no "vhdl-mode maintainer" other than the vhdl-mode author.  If
you have patches that implement what you requested above, please send
them to bug-gnu-emacs@gnu.org and they will get installed. 

bug#5136: Request to update vhdl-mode and verilog-mode

[Reto Zimmermann]

Chitlesh GOORAH wrote:

> Similarly, for vhdl-mode (included within emacs sources), weirdly does
> not support ghdl or freehdl out of the box, but only proprietary
> simulators. Can your vhdl-mode maintainer for emacs can fix it and put
> ghdl as default simulator please ?

Please send me the required information and I will include them.

  Compiler name    : name used in option `vhdl-compiler' to choose compiler
  Compile command  : command used for source file compilation
  Compile options  : compile options (\"\\1\" inserts library name)
  Library command  : command to create library directory \(\"\\1\" inserts
                     library directory, \"\\2\" inserts library name)
  Library directory: directory of default library
Error message:
  Regexp           : regular expression to match error messages (*)
  File subexp index: index of subexpression that matches the file name
  Line subexp index: index of subexpression that matches the line number
  Column subexp idx: index of subexpression that matches the column number
File message:
  Regexp           : regular expression to match a file name message
  File subexp index: index of subexpression that matches the file name
Unit-to-file name mapping: mapping of library unit names to names of files
                     generated by the compiler (used for Makefile generation)
  To string        : string a name is mapped to (\"\\1\" inserts the unit name,
                     \"\\2\" inserts the entity name for architectures)
  Case adjustment  : adjust case of inserted unit names

Reto

bug#5136: Request to update vhdl-mode and verilog-mode

[Chitlesh GOORAH]

Hello there,

First, I'm an emacs user since a week now. So I'm still learning the
internals. However, I've just created a patch for ghdl and fixes some
compilation warnings.

http://chitlesh.fedorapeople.org/emacs/emacs-vhdl-mode-ghdl.patch
Which seems to work for me and it can generate a proper makefile.

However I can't figure out how to tell it that if a testbench is
provided, then add the following lines to the Makefile

ghdl -m --workdir=work/ --ieee=synopsys -fexplicit $(TESTBENCH)
ghdl -r  $(PROJECT)_tb --vcd=$(PROJECT).vcd --stop-time=$(STOPTIME_US)

Chitlesh


On Tue, Dec 8, 2009 at 5:37 PM, Reto Zimmermann <reto@gnu.org> wrote:
> Chitlesh GOORAH wrote:
>
>> Similarly, for vhdl-mode (included within emacs sources), weirdly does
>> not support ghdl or freehdl out of the box, but only proprietary
>> simulators. Can your vhdl-mode maintainer for emacs can fix it and put
>> ghdl as default simulator please ?

>
> Please send me the required information and I will include them.
>
>  Compiler name    : name used in option `vhdl-compiler' to choose compiler
>  Compile command  : command used for source file compilation
>  Compile options  : compile options (\"\\1\" inserts library name)
>  Library command  : command to create library directory \(\"\\1\" inserts
>                    library directory, \"\\2\" inserts library name)
>  Library directory: directory of default library
> Error message:
>  Regexp           : regular expression to match error messages (*)
>  File subexp index: index of subexpression that matches the file name
>  Line subexp index: index of subexpression that matches the line number
>  Column subexp idx: index of subexpression that matches the column number
> File message:
>  Regexp           : regular expression to match a file name message
>  File subexp index: index of subexpression that matches the file name
> Unit-to-file name mapping: mapping of library unit names to names of files
>                    generated by the compiler (used for Makefile generation)
>  To string        : string a name is mapped to (\"\\1\" inserts the unit
> name,
>                    \"\\2\" inserts the entity name for architectures)
>  Case adjustment  : adjust case of inserted unit names
>
> Reto
>
>

bug#5136: Request to update vhdl-mode and verilog-mode

[Reto Zimmermann]

Chitlesh,

I added your settings for GHDL to the upcoming vhdl-mode version 3.33.28.  I'm still holding it because I first have to resolve some issues with the new compile.el in Emacs 23.

I am aware of the compilation warnings but I'm not applying the fixes to my version because they break older Emacs versions as well as XEmacs.  I'm trying to keep my vhdl-mode version compatible with recent Emacs and XEmacs versions.

You should be able to add the lines to Makefile using the hook vhdl-makefile-generation-hook.

Reto


Chitlesh GOORAH wrote:
> Hello there,
> 
> First, I'm an emacs user since a week now. So I'm still learning the
> internals. However, I've just created a patch for ghdl and fixes some
> compilation warnings.
> 
> http://chitlesh.fedorapeople.org/emacs/emacs-vhdl-mode-ghdl.patch
> Which seems to work for me and it can generate a proper makefile.
> 
> However I can't figure out how to tell it that if a testbench is
> provided, then add the following lines to the Makefile
> 
> ghdl -m --workdir=work/ --ieee=synopsys -fexplicit $(TESTBENCH)
> ghdl -r  $(PROJECT)_tb --vcd=$(PROJECT).vcd --stop-time=$(STOPTIME_US)
> 
> Chitlesh
> 
> 
> On Tue, Dec 8, 2009 at 5:37 PM, Reto Zimmermann <reto@gnu.org> wrote:
>> Chitlesh GOORAH wrote:
>>
>>> Similarly, for vhdl-mode (included within emacs sources), weirdly does
>>> not support ghdl or freehdl out of the box, but only proprietary
>>> simulators. Can your vhdl-mode maintainer for emacs can fix it and put
>>> ghdl as default simulator please ?
> 
>> Please send me the required information and I will include them.
>>
>>  Compiler name    : name used in option `vhdl-compiler' to choose compiler
>>  Compile command  : command used for source file compilation
>>  Compile options  : compile options (\"\\1\" inserts library name)
>>  Library command  : command to create library directory \(\"\\1\" inserts
>>                    library directory, \"\\2\" inserts library name)
>>  Library directory: directory of default library
>> Error message:
>>  Regexp           : regular expression to match error messages (*)
>>  File subexp index: index of subexpression that matches the file name
>>  Line subexp index: index of subexpression that matches the line number
>>  Column subexp idx: index of subexpression that matches the column number
>> File message:
>>  Regexp           : regular expression to match a file name message
>>  File subexp index: index of subexpression that matches the file name
>> Unit-to-file name mapping: mapping of library unit names to names of files
>>                    generated by the compiler (used for Makefile generation)
>>  To string        : string a name is mapped to (\"\\1\" inserts the unit
>> name,
>>                    \"\\2\" inserts the entity name for architectures)
>>  Case adjustment  : adjust case of inserted unit names
>>
>> Reto
>>
>>
> 

bug#5136: Request to update vhdl-mode and verilog-mode

[Chitlesh GOORAH]

On Wed, Dec 16, 2009 at 2:21 PM, Reto Zimmermann <reto@gnu.org> wrote:
> Chitlesh,
>
> I added your settings for GHDL to the upcoming vhdl-mode version 3.33.28.
>  I'm still holding it because I first have to resolve some issues with the
> new compile.el in Emacs 23.
>
> I am aware of the compilation warnings but I'm not applying the fixes to my
> version because they break older Emacs versions as well as XEmacs.  I'm
> trying to keep my vhdl-mode version compatible with recent Emacs and XEmacs
> versions.
>
> You should be able to add the lines to Makefile using the hook
> vhdl-makefile-generation-hook.
>

Thank you.
I'm looking forward for the next release.

Cheers,
Chitlesh

bug#5136: Request to update vhdl-mode and verilog-mode

[Glenn Morris]

Version: 24.4

As of now, both are up-to-date.

bug#5136: Request to update vhdl-mode and verilog-mode

[Reto Zimmermann]

Dan Nicolaescu wrote:
> Chitlesh GOORAH <chitlesh.goorah@gmail.com> writes:
> 
>   > Hello there,
>   > 
>   > The following modes bundled in emacs-23.1-13.fc12.i686 are very old
>   > compared to the lastest upstream releases.
>   > 
>   > vhdl-mode
>   > http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html
> 
> Reto can you please send a patch + ChangeLog for the changes?

Unfortunately vhdl-mode in the repository and my version have diverged again.  The main reason is that I have to keep my version compatible with older emacs releases as well as with XEmacs, so I wasn't able to apply all changes done in the repository version.  It would be a non-trivial task to merge the versions again.

Reto

bug#5136: Request to update vhdl-mode and verilog-mode

[Stefan Monnier]

>> > Hello there,
>> >   > The following modes bundled in emacs-23.1-13.fc12.i686 are very
>> >   > old compared to the lastest upstream releases.
>> >   > vhdl-mode
>> > http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html
>> Reto can you please send a patch + ChangeLog for the changes?
> Unfortunately vhdl-mode in the repository and my version have diverged
> again.  The main reason is that I have to keep my version compatible
> with older Emacs releases as well as with XEmacs, so I wasn't able to
> apply all changes done in the repository version.  It would be
> a non-trivial task to merge the versions again.

I'd guess that emacs-devel people (those responsiable for the changes
in Emacs-CVS) can help you do that.  Can you send us a "diff3 -A" merged
version of the file, so we can help you resolve the conflicts?

Of course, a better approach would be to keep the official release
directly in the Emacs-CVS, so merge problems have to be handled earlier,
when they're easier to address.


        Stefan