From: Nicolas Matringe <nicolas.matringe@fre.fre>
To: help-gnu-emacs@gnu.org
Subject: Re: How to disable "_i" insertion on signals in emacs VHDL mode
Date: Wed, 31 Jan 2007 22:13:54 +0100 [thread overview]
Message-ID: <45c1066a$0$29467$426a74cc@news.free.fr> (raw)
In-Reply-To: <1170273536.940804.311030@k78g2000cwa.googlegroups.com>
chris.plachta@gmail.com a écrit :
> Hi,
>
> Does anyone know how to disable the automatic insertion of "_i" on
> signals that are connect to a instance port map?
>
> For example, when I use the vhdl-paste-port-instance command on a
> model with the ports called "rst_l" and "clk", it gives me this:
>
>
> instance: clk_model
> port map (
> rst_l => rst_l_i,
> clk => clk_i);
>
> I want to get rid of the "_i" convention and use identical names for
> the port and the signal.
Hi
I still don't know the actual variable name ...
See VHDL>Options>Port>Actual Port Names...
Nicolas
next prev parent reply other threads:[~2007-01-31 21:13 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-01-31 19:58 How to disable "_i" insertion on signals in emacs VHDL mode chris.plachta
2007-01-31 21:13 ` Nicolas Matringe [this message]
2007-02-01 3:13 ` Mike Treseler
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