VHDL projects in emacs

VHDL projects in emacs

[jerzy.gbur]

Hello,
I'm FPGA designer, I work on Xilinx ISE tools (MS Windows XP).
I've started to use emacs a week ago. It looks very impressive.

But..
1. How can I organize working with projects? I have some projects
added to environment through putting their definition in .emacs file.
It looks messy for me. How can I do other way? How you do that?

2. Is there possibility to mark column region for copy/cut?

Best Regards,

Jerzy Gbur

RE: VHDL projects in emacs

[Drew Adams]

> 1. How can I organize working with projects? I have some projects
> added to environment through putting their definition in .emacs file.
> It looks messy for me. How can I do other way? How you do that?

http://www.emacswiki.org/cgi-bin/wiki/CategoryProgrammerUtils#ProjectSupport

> 2. Is there possibility to mark column region for copy/cut?

http://www.emacswiki.org/cgi-bin/wiki/CuaMode 

And see the Emacs manual, node CUA Bindings.

Re: VHDL projects in emacs

[Juanma]

On Wednesday 02 July 2008, Drew Adams wrote:
> > 2. Is there possibility to mark column region for copy/cut?
> 
> http://www.emacswiki.org/cgi-bin/wiki/CuaMode 
> 
> And see the Emacs manual, node CUA Bindings.

Or, using the (real) Emacs rectangle commands, the region is marked as
usual (and the highlighted region is not rectangular) but the rectangle
commands apply only to the rectangular area defined by mark and point.
See: M-x apropos RET rectangle

Pozdrawiam / Best regards.
--
Juanma