* confused by emacs verilog mode
@ 2014-05-24 7:51 chenyong20000
2014-05-25 6:57 ` chenyong20000
0 siblings, 1 reply; 6+ messages in thread
From: chenyong20000 @ 2014-05-24 7:51 UTC (permalink / raw)
To: help-gnu-emacs
Hi,
I'm trying to use emacs verilog mode for vi. I have a piece of code like this:
fifo_half_entry AUTO_TEMPLATE (
.shift_datain_r (dataout0_r_entry_@"(+ 1 @)"),
.shift_datain_f (dataout0_f_entry_@"(+ 1 @)"),
.dataout_r (dataout0_r_entry_@),
.dataout_f (dataout0_f_entry_@),
.datain_r (rddata_in_r[3:0]),
.datain_f (rddata_in_f[3:0]),
.fifo_write (fifo_write0_@),
.fifo_shift (gather_pop),
.rst_n (rst_n_propgt),
.clear_fifo (clear_fifo_R),
);
*/
fifo_half_entry inst_gather_fifol_entry_0 (/*AUTOINST*/);
fifo_half_entry inst_gather_fifol_entry_1 (/*AUTOINST*/);
fifo_half_entry inst_gather_fifol_entry_2 (/*AUTOINST*/);
fifo_half_entry inst_gather_fifol_entry_3 (/*AUTOINST*/);
fifo_half_entry inst_gather_fifol_entry_4 (/*AUTOINST*/);
/* fifo_half_entry AUTO_TEMPLATE (
.shift_datain_r (dataout1_r_entry_@"(+ 1 @)"),
.shift_datain_f (dataout1_f_entry_@"(+ 1 @)"),
.dataout_r (dataout1_r_entry_@),
.dataout_f (dataout1_f_entry_@),
.datain_r (rddata_in_r[7:4]),
.datain_f (rddata_in_f[7:4]),
.fifo_write (fifo_write1_@),
.fifo_shift (gather_pop),
.rst_n (rst_n_propgt),
.clear_fifo (clear_fifo_R),
);
*/
fifo_half_entry inst_gather_fifoh_entry_0 (/*AUTOINST*/);
fifo_half_entry inst_gather_fifoh_entry_1 (/*AUTOINST*/);
fifo_half_entry inst_gather_fifoh_entry_2 (/*AUTOINST*/);
fifo_half_entry inst_gather_fifoh_entry_3 (/*AUTOINST*/);
fifo_half_entry inst_gather_fifoh_entry_4 (/*AUTOINST*/);
what confused me is that after generate code, it seems like this:
fifo_half_entry AUTO_TEMPLATE (
.shift_datain_r (dataout0_r_entry_@"(+ 1 @)"),
.shift_datain_f (dataout0_f_entry_@"(+ 1 @)"),
.dataout_r (dataout0_r_entry_@),
.dataout_f (dataout0_f_entry_@),
.datain_r (rddata_in_r[3:0]),
.datain_f (rddata_in_f[3:0]),
.fifo_write (fifo_write0_@),
.fifo_shift (gather_pop),
.rst_n (rst_n_propgt),
.clear_fifo (clear_fifo_R),
);
*/
fifo_half_entry inst_gather_fifol_entry_0 (/*AUTOINST*/
// Outputs
.dataout_r (dataout1_r_entry_0), // Templated
.dataout_f (dataout1_f_entry_0), // Templated
// Inputs
.clk (clk),
.rst_n (rst_n_propgt), // Templated
.datain_r (rddata_in_r[7:4]), // Templated
.datain_f (rddata_in_f[7:4]), // Templated
.shift_datain_r (dataout1_r_entry_1), // Templated
.shift_datain_f (dataout1_f_entry_1), // Templated
.fifo_write (fifo_write1_0), // Templated
.fifo_shift (gather_pop), // Templated
.clear_fifo (clear_fifo_R)); // Templated
fifo_half_entry inst_gather_fifol_entry_1 (/*AUTOINST*/
// Outputs
.dataout_r (dataout1_r_entry_1), // Templated
.dataout_f (dataout1_f_entry_1), // Templated
// Inputs
.clk (clk),
.rst_n (rst_n_propgt), // Templated
you can find from these code that the dataout0_r_entry_xxx has been changed from dataout0 to dataout1. I don't know how this happens and how can i get right code. Can anybody help me? thanks.
regards
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: confused by emacs verilog mode
2014-05-24 7:51 confused by emacs verilog mode chenyong20000
@ 2014-05-25 6:57 ` chenyong20000
2014-05-25 19:36 ` Stefan Monnier
[not found] ` <mailman.2075.1401046828.1147.help-gnu-emacs@gnu.org>
0 siblings, 2 replies; 6+ messages in thread
From: chenyong20000 @ 2014-05-25 6:57 UTC (permalink / raw)
To: help-gnu-emacs
在 2014年5月24日星期六UTC+8下午3时51分31秒,chenyo...@gmail.com写道:
> Hi,
>
>
>
> I'm trying to use emacs verilog mode for vi. I have a piece of code like this:
>
>
>
> fifo_half_entry AUTO_TEMPLATE (
>
> .shift_datain_r (dataout0_r_entry_@"(+ 1 @)"),
>
> .shift_datain_f (dataout0_f_entry_@"(+ 1 @)"),
>
> .dataout_r (dataout0_r_entry_@),
>
> .dataout_f (dataout0_f_entry_@),
>
> .datain_r (rddata_in_r[3:0]),
>
> .datain_f (rddata_in_f[3:0]),
>
> .fifo_write (fifo_write0_@),
>
> .fifo_shift (gather_pop),
>
> .rst_n (rst_n_propgt),
>
> .clear_fifo (clear_fifo_R),
>
> );
>
> */
>
> fifo_half_entry inst_gather_fifol_entry_0 (/*AUTOINST*/);
>
> fifo_half_entry inst_gather_fifol_entry_1 (/*AUTOINST*/);
>
> fifo_half_entry inst_gather_fifol_entry_2 (/*AUTOINST*/);
>
> fifo_half_entry inst_gather_fifol_entry_3 (/*AUTOINST*/);
>
> fifo_half_entry inst_gather_fifol_entry_4 (/*AUTOINST*/);
>
> /* fifo_half_entry AUTO_TEMPLATE (
>
> .shift_datain_r (dataout1_r_entry_@"(+ 1 @)"),
>
> .shift_datain_f (dataout1_f_entry_@"(+ 1 @)"),
>
> .dataout_r (dataout1_r_entry_@),
>
> .dataout_f (dataout1_f_entry_@),
>
> .datain_r (rddata_in_r[7:4]),
>
> .datain_f (rddata_in_f[7:4]),
>
> .fifo_write (fifo_write1_@),
>
> .fifo_shift (gather_pop),
>
> .rst_n (rst_n_propgt),
>
> .clear_fifo (clear_fifo_R),
>
> );
>
> */
>
> fifo_half_entry inst_gather_fifoh_entry_0 (/*AUTOINST*/);
>
> fifo_half_entry inst_gather_fifoh_entry_1 (/*AUTOINST*/);
>
> fifo_half_entry inst_gather_fifoh_entry_2 (/*AUTOINST*/);
>
> fifo_half_entry inst_gather_fifoh_entry_3 (/*AUTOINST*/);
>
> fifo_half_entry inst_gather_fifoh_entry_4 (/*AUTOINST*/);
>
>
>
> what confused me is that after generate code, it seems like this:
>
>
>
> fifo_half_entry AUTO_TEMPLATE (
>
> .shift_datain_r (dataout0_r_entry_@"(+ 1 @)"),
>
> .shift_datain_f (dataout0_f_entry_@"(+ 1 @)"),
>
> .dataout_r (dataout0_r_entry_@),
>
> .dataout_f (dataout0_f_entry_@),
>
> .datain_r (rddata_in_r[3:0]),
>
> .datain_f (rddata_in_f[3:0]),
>
> .fifo_write (fifo_write0_@),
>
> .fifo_shift (gather_pop),
>
> .rst_n (rst_n_propgt),
>
> .clear_fifo (clear_fifo_R),
>
> );
>
> */
>
> fifo_half_entry inst_gather_fifol_entry_0 (/*AUTOINST*/
>
> // Outputs
>
> .dataout_r (dataout1_r_entry_0), // Templated
>
> .dataout_f (dataout1_f_entry_0), // Templated
>
> // Inputs
>
> .clk (clk),
>
> .rst_n (rst_n_propgt), // Templated
>
> .datain_r (rddata_in_r[7:4]), // Templated
>
> .datain_f (rddata_in_f[7:4]), // Templated
>
> .shift_datain_r (dataout1_r_entry_1), // Templated
>
> .shift_datain_f (dataout1_f_entry_1), // Templated
>
> .fifo_write (fifo_write1_0), // Templated
>
> .fifo_shift (gather_pop), // Templated
>
> .clear_fifo (clear_fifo_R)); // Templated
>
> fifo_half_entry inst_gather_fifol_entry_1 (/*AUTOINST*/
>
> // Outputs
>
> .dataout_r (dataout1_r_entry_1), // Templated
>
> .dataout_f (dataout1_f_entry_1), // Templated
>
> // Inputs
>
> .clk (clk),
>
> .rst_n (rst_n_propgt), // Templated
>
>
>
>
>
> you can find from these code that the dataout0_r_entry_xxx has been changed from dataout0 to dataout1. I don't know how this happens and how can i get right code. Can anybody help me? thanks.
>
>
>
>
>
> regards
Can anybody give me some suggestion? thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: confused by emacs verilog mode
2014-05-25 6:57 ` chenyong20000
@ 2014-05-25 19:36 ` Stefan Monnier
[not found] ` <mailman.2075.1401046828.1147.help-gnu-emacs@gnu.org>
1 sibling, 0 replies; 6+ messages in thread
From: Stefan Monnier @ 2014-05-25 19:36 UTC (permalink / raw)
To: help-gnu-emacs
>> I'm trying to use emacs verilog mode for vi. I have a piece of code
>> like this:
[...]
>> what confused me is that after generate code, it seems like this:
[...]
>> you can find from these code that the dataout0_r_entry_xxx has been
>> changed from dataout0 to dataout1. I don't know how this happens and
>> how can i get right code. Can anybody help me? thanks.
You say "after generate code", but I have no idea what that step
refers to. What makes you think this has to do with Emacs?
Stefan
^ permalink raw reply [flat|nested] 6+ messages in thread
[parent not found: <mailman.2075.1401046828.1147.help-gnu-emacs@gnu.org>]
* Re: confused by emacs verilog mode
[not found] ` <mailman.2075.1401046828.1147.help-gnu-emacs@gnu.org>
@ 2014-05-26 1:05 ` chenyong20000
2014-05-26 2:20 ` chenyong20000
0 siblings, 1 reply; 6+ messages in thread
From: chenyong20000 @ 2014-05-26 1:05 UTC (permalink / raw)
To: help-gnu-emacs
在 2014年5月26日星期一UTC+8上午3时36分00秒,Stefan Monnier写道:
> >> I'm trying to use emacs verilog mode for vi. I have a piece of code
>
> >> like this:
>
> [...]
>
> >> what confused me is that after generate code, it seems like this:
>
> [...]
>
> >> you can find from these code that the dataout0_r_entry_xxx has been
>
> >> changed from dataout0 to dataout1. I don't know how this happens and
>
> >> how can i get right code. Can anybody help me? thanks.
>
>
>
> You say "after generate code", but I have no idea what that step
>
> refers to. What makes you think this has to do with Emacs?
>
>
>
>
>
> Stefan
Hi Stefan,
in fact the editor is vi, but company IT has embedded some scripts so that the vi could use those features for emacs. The vi works fine with other files, but failed on these pieces of code. Why do you think this has no relation to emacs?Thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: confused by emacs verilog mode
2014-05-26 1:05 ` chenyong20000
@ 2014-05-26 2:20 ` chenyong20000
2014-05-26 6:41 ` Thien-Thi Nguyen
0 siblings, 1 reply; 6+ messages in thread
From: chenyong20000 @ 2014-05-26 2:20 UTC (permalink / raw)
To: help-gnu-emacs
在 2014年5月26日星期一UTC+8上午9时05分51秒,chenyo...@gmail.com写道:
> 在 2014年5月26日星期一UTC+8上午3时36分00秒,Stefan Monnier写道:
>
> > >> I'm trying to use emacs verilog mode for vi. I have a piece of code
>
> >
>
> > >> like this:
>
> >
>
> > [...]
>
finally I found the root reason. Thanks.
> >
>
> > >> what confused me is that after generate code, it seems like this:
>
> >
>
> > [...]
>
> >
>
> > >> you can find from these code that the dataout0_r_entry_xxx has been
>
> >
>
> > >> changed from dataout0 to dataout1. I don't know how this happens and
>
> >
>
> > >> how can i get right code. Can anybody help me? thanks.
>
> >
>
> >
>
> >
>
> > You say "after generate code", but I have no idea what that step
>
> >
>
> > refers to. What makes you think this has to do with Emacs?
>
> >
>
> >
>
> >
>
> >
>
> >
>
> > Stefan
>
>
>
> Hi Stefan,
>
> in fact the editor is vi, but company IT has embedded some scripts so that the vi could use those features for emacs. The vi works fine with other files, but failed on these pieces of code. Why do you think this has no relation to emacs?Thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-05-26 6:41 UTC | newest]
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2014-05-24 7:51 confused by emacs verilog mode chenyong20000
2014-05-25 6:57 ` chenyong20000
2014-05-25 19:36 ` Stefan Monnier
[not found] ` <mailman.2075.1401046828.1147.help-gnu-emacs@gnu.org>
2014-05-26 1:05 ` chenyong20000
2014-05-26 2:20 ` chenyong20000
2014-05-26 6:41 ` Thien-Thi Nguyen
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