Re: Untagging by subtraction instead of masking on USE_LSB_TAG

[Stefan Monnier <monnier@iro.umontreal.ca>]

> This would make sense if the latency of load/store does not depend on
> its displacement (I'm not sure if that is the case in general).
> Comments?

Yes, all RISC processors I can think of (other than ADM29K, maybe)
provide a "small" offset for free: a 0 offset is no faster than
a -5 offset.

Additionally, masking the lower 3 bits may sometimes be surprisingly
costly (the obvious solution of ANDing with ~7 requires a 32bit
constant, which tends to be more costly than a smaller constant, and
the rsh+lsh can be even worse).

So, yes, your patch looks like a very good idea in general.
It's also what is typically used in Lisp/Smalltalk/younameit compilers.


        Stefan


PS: This trick has another advantage: on some hardware (e.g. SPARC) if
after adding/subtracting the offset, the resulting address is not
aligned, you can get an exception, which means you get tag-checking for
free.  This is no coincidence, since the SPARC architecture benefitted
from the experience of the SOAR (Smalltalk On A RISC) project.