Help fix unescaped character literals detected warnings in verilog-mode (Was: Re: "unescaped character literals detected")

[Kaushal Modi <kaushal.modi@gmail.com>]

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On Fri, May 5, 2017 at 3:49 PM Kaushal Modi <kaushal.modi@gmail.com> wrote:

> verilog-mode.el has 14.5k lines. It would be very helpful to print the
> line number where unescapted character literals are detected so that I can
> attempt to fix it.
>

A quick followup:

I byte-compiled verilog-mode.el, and it throws these warnings:

verilog-mode.el:14003:1:Warning: unescaped character literals ; detected!
verilog-mode.el:14013:1:Warning: unescaped character literals ; detected!
verilog-mode.el:14205:1:Warning: unescaped character literals ; detected!

I believe that the compiler does not like lines like

> "task " '(verilog-sk-prompt-name) & ?; \n

Changing that to the below fixes the warning:

> "task " '(verilog-sk-prompt-name) & \?; \n


But I am not familiar with the define-skeleton syntax. Does anyone know if
changing "?" to "\?" in the below 3 instances of skeleton definitions would
be fine?

On line 14003, there is:

(define-skeleton verilog-sk-task
  "Insert a task definition."
  ()
  > "task " '(verilog-sk-prompt-name) & ?; \n
  > _ \n
  > "begin" \n
  > \n
  > (- verilog-indent-level-behavioral) "end" \n
  > (- verilog-indent-level-behavioral) "endtask" (progn
(electric-verilog-terminate-line) nil))

On line 14013, there is:

(define-skeleton verilog-sk-function
  "Insert a function definition."
  ()
  > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name)
?; \n
  > _ \n
  > "begin" \n
  > \n
  > (- verilog-indent-level-behavioral) "end" \n
  > (- verilog-indent-level-behavioral) "endfunction" (progn
(electric-verilog-terminate-line) nil))

On line 14205, there is:

(define-skeleton verilog-sk-state-machine
  "Insert a state machine definition."
  "Name of state variable: "
  '(setq input "state")
  > "// State registers for " str | -23 \n
  '(setq verilog-sk-state str)
  > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_"
verilog-sk-state ?; \n
  '(setq input nil)
  > \n
  > "// State FF for " verilog-sk-state \n
  > "always @ ( " (read-string "clock:" "posedge clk") " or "
(verilog-sk-prompt-reset) " ) begin" \n
  > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
  > verilog-sk-state " = next_" verilog-sk-state ?; \n
  > (- verilog-indent-level-behavioral) "end" (progn
(electric-verilog-terminate-line) nil)
  > \n
  > "// Next State Logic for " verilog-sk-state \n
  > "always @ ( /*AUTOSENSE*/ ) begin\n"
  > "case (" '(verilog-sk-prompt-state-selector) ") " \n
  > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _
";" \n > (- verilog-indent-level-behavioral) "end" \n )
  resume: >  (- verilog-case-indent) "endcase" (progn
(electric-verilog-terminate-line) nil)
  > (- verilog-indent-level-behavioral) "end" (progn
(electric-verilog-terminate-line) nil))

-- 

Kaushal Modi

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