From: Friedrich Beckmann <friedrich.beckmann@gmx.de>
To: 5768@debbugs.gnu.org
Cc: Reto Zimmermann <reto@gnu.org>
Subject: bug#5768: vhdl-mode.el: modelsim error parsing does not work. Patch attached.
Date: Fri, 31 Oct 2014 17:32:50 +0100 [thread overview]
Message-ID: <70998565-3312-4466-8210-4AE60055C737@gmx.de> (raw)
In-Reply-To: <521D0D1B5A27F542B4CD0401CB20AF0A3DF849@nhc0ex20.goodrich.root.local>
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Control: Tags -1 patch
Hi,
I can confirm that the problem with modelsim error parsing in VHDL mode is still there
in Ubuntu 14.04 with Emacs version 24.3.1 and vhdl-mode.el from the current gnu emacs
repository and also the original ubuntu vhdl-mode.elc version 3.33.28.
I fixed the problem by modifying vhdl-mode.el file from the current repository. The patch is attached.
By the way, the upstream link:
http://www.iis.ee.ethz.ch/~zimmi
is a dead link today. Attached are two pictures showing emacs before and after the fix and the patch of vhdl-mode.el.
Friedrich
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diff --git a/lisp/progmodes/vhdl-mode.el b/lisp/progmodes/vhdl-mode.el
index 3d5a398..7c51587 100644
--- a/lisp/progmodes/vhdl-mode.el
+++ b/lisp/progmodes/vhdl-mode.el
@@ -264,9 +264,14 @@ Overrides local variable `indent-tabs-mode'."
;; WARNING[2]: test.vhd(85): Possible infinite loop
;; ** Warning: [4] ../src/emacsvsim.vhd(43): An abstract ...
;; ** Error: adder.vhd(190): Unknown identifier: ctl_numb
+ ;; ** Error: counter_rtl.vhd(18): Nonresolved signal 'hallo' has multiple sources.
+ ;; Drivers:
+ ;; counter_rtl.vhd(27):Conditional signal assignment line__27
+ ;; counter_rtl.vhd(29):Conditional signal assignment line__29
("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1"
nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim"
- ("\\(ERROR\\|WARNING\\|\\*\\* Error\\|\\*\\* Warning\\)[^:]*:\\( *\[[0-9]+\]\\)? \\([^ \\t\\n]+\\)(\\([0-9]+\\)):" 3 4 nil) ("" 0)
+ ("\\(ERROR:\\|WARNING\\[[0-9]+\\]:\\|\\*\\* Error:\\|\\*\\* Warning: \\[[0-9]+\\]\\| +\\) \\([^ ]+\\)(\\([0-9]+\\)):" 2 3 nil)
+ ("" 0)
("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat"
"\\1/_primary.dat" "\\1/body.dat" downcase))
;; ProVHDL, Synopsys LEDA: provhdl -w work -f test.vhd
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next prev parent reply other threads:[~2014-10-31 16:32 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-03-24 15:51 bug#5768: 23.1; ModelSim and compile.el Scott, Ashley
2010-03-24 20:59 ` Stefan Monnier
2010-03-25 11:44 ` Scott, Ashley
2014-10-31 16:32 ` Friedrich Beckmann [this message]
2014-11-01 19:49 ` bug#5768: Bug 5768: vhdl-mode.el: Modelsim error parsing patch in plain text Friedrich Beckmann
2016-02-28 6:05 ` Lars Ingebrigtsen
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